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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 09:16:13 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 09:16:13 -0700 |
| commit | 2168568f43984af2d194c0eab74ad73443f7e84c (patch) | |
| tree | 84204a170894df07c0f52a32941ab81493664450 /techlibs/common | |
| parent | bddd641290d3c01d86144362cd0e16c82e0bcfd8 (diff) | |
| download | yosys-2168568f43984af2d194c0eab74ad73443f7e84c.tar.gz yosys-2168568f43984af2d194c0eab74ad73443f7e84c.tar.bz2 yosys-2168568f43984af2d194c0eab74ad73443f7e84c.zip | |
Use sign_headroom instead
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 1f4759929..da887d426 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -108,7 +108,7 @@ module \$__mul_gen (A, B, Y); end
\$__mul_gen #(
- .A_SIGNED(0),
+ .A_SIGNED(sign_headroom),
.B_SIGNED(B_SIGNED),
.A_WIDTH(`DSP_A_MAXWIDTH),
.B_WIDTH(B_WIDTH),
@@ -122,7 +122,7 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice
\$__mul_gen #(
- .A_SIGNED(0),
+ .A_SIGNED(sign_headroom),
.B_SIGNED(B_SIGNED),
.A_WIDTH(`DSP_A_MAXWIDTH),
.B_WIDTH(B_WIDTH),
@@ -163,7 +163,7 @@ module \$__mul_gen (A, B, Y); \$__mul_gen #(
.A_SIGNED(A_SIGNED),
- .B_SIGNED(0),
+ .B_SIGNED(sign_headroom),
.A_WIDTH(A_WIDTH),
.B_WIDTH(`DSP_B_MAXWIDTH),
.Y_WIDTH(partial_Y_WIDTH)
@@ -177,7 +177,7 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice
\$__mul_gen #(
.A_SIGNED(A_SIGNED),
- .B_SIGNED(0),
+ .B_SIGNED(sign_headroom),
.A_WIDTH(A_WIDTH),
.B_WIDTH(`DSP_B_MAXWIDTH),
.Y_WIDTH(partial_Y_WIDTH)
|