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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 09:50:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 09:50:47 -0700 |
| commit | acfb672d34092d67b0b3ed6a6ab45e5aac8e2bc0 (patch) | |
| tree | d508df4d2b0c85ddc4920de5082d532abd684bc7 /techlibs/common | |
| parent | 5aef998957c00f1d7e5991d0c1122f49751d7311 (diff) | |
| download | yosys-acfb672d34092d67b0b3ed6a6ab45e5aac8e2bc0.tar.gz yosys-acfb672d34092d67b0b3ed6a6ab45e5aac8e2bc0.tar.bz2 yosys-acfb672d34092d67b0b3ed6a6ab45e5aac8e2bc0.zip | |
A bit more on where $lcu comes from
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simlib.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index f16866e86..1b172c112 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -537,6 +537,8 @@ endmodule // used in binary arithmetic operations. By replacing the ripple // carry structure used in full-adder blocks, the more significant // bits of the sum can be expected to be computed more quickly. +// Typically created during `techmap` of $alu cells +// (see the "_90_alu" rule in +/techmap.v) module \$lcu (P, G, CI, CO); parameter WIDTH = 1; |