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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 14:29:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 14:29:00 -0700 |
| commit | 65de9aaaa9d744686e235ff8701cd997cd2dc891 (patch) | |
| tree | 94209344c0d904684102e5b15e3d4fbb0cd9a459 /techlibs/common | |
| parent | 915f4e34bfdf1fd2b9f97d1c15a55e2c4c49f428 (diff) | |
| download | yosys-65de9aaaa9d744686e235ff8701cd997cd2dc891.tar.gz yosys-65de9aaaa9d744686e235ff8701cd997cd2dc891.tar.bz2 yosys-65de9aaaa9d744686e235ff8701cd997cd2dc891.zip | |
Add DSP_SIGNEDONLY back
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 5ff0e03aa..6cd5128a6 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -55,6 +55,22 @@ module \$mul (A, B, Y); if (A_SIGNED != B_SIGNED)
wire _TECHMAP_FAIL_ = 1;
// NB: A_SIGNED == B_SIGNED from here
+`ifdef DSP_SIGNEDONLY
+ else if (!A_SIGNED) begin
+ wire [1:0] _;
+ \$mul #(
+ .A_SIGNED(1),
+ .B_SIGNED(1),
+ .A_WIDTH(A_WIDTH + 1),
+ .B_WIDTH(B_WIDTH + 1),
+ .Y_WIDTH(Y_WIDTH + 2)
+ ) _TECHMAP_REPLACE_ (
+ .A({1'b0, A}),
+ .B({1'b0, B}),
+ .Y({_, Y})
+ );
+ end
+`endif
else if (A_WIDTH < B_WIDTH)
\$mul #(
.A_SIGNED(B_SIGNED),
|