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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 12:17:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 12:17:14 -0700 |
| commit | 332b86491de4d033f2fe259ab7ad7d02761cc515 (patch) | |
| tree | 7486c2586f203569e54f6e060e89e03e27681ac5 /techlibs/common | |
| parent | ed303b07b770c6aa4bc69f04bc517ce4701988ed (diff) | |
| download | yosys-332b86491de4d033f2fe259ab7ad7d02761cc515.tar.gz yosys-332b86491de4d033f2fe259ab7ad7d02761cc515.tar.bz2 yosys-332b86491de4d033f2fe259ab7ad7d02761cc515.zip | |
Revert "Do not do sign extension in techmap; let packer do it"
This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd.
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index b28a4247e..99afce18c 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -232,15 +232,24 @@ module \$__mul (A, B, Y); assign Y = partial_sum[n-1];
end
else begin
+ if (A_SIGNED)
+ wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
+ else
+ wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
+ if (B_SIGNED)
+ wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
+ else
+ wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
+
`DSP_NAME #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
- .A_WIDTH(A_WIDTH),
- .B_WIDTH(B_WIDTH),
- .Y_WIDTH(`MIN(Y_WIDTH,A_WIDTH+B_WIDTH)),
+ .A_WIDTH(`DSP_A_MAXWIDTH),
+ .B_WIDTH(`DSP_B_MAXWIDTH),
+ .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
) _TECHMAP_REPLACE_ (
- .A(A),
- .B(B),
+ .A(Aext),
+ .B(Bext),
.Y(Y)
);
end
|