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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-13 16:52:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-13 16:52:15 -0700 |
| commit | e35dfc5ab591968d86259b90a643f1545e79e661 (patch) | |
| tree | 80f68bc289d5257c9677664f91e84b704b85dcb6 /techlibs/common | |
| parent | ed4b2834ef6ed811318c897bd6f8b19b6ec15f38 (diff) | |
| download | yosys-e35dfc5ab591968d86259b90a643f1545e79e661.tar.gz yosys-e35dfc5ab591968d86259b90a643f1545e79e661.tar.bz2 yosys-e35dfc5ab591968d86259b90a643f1545e79e661.zip | |
Only swap ports if $mul and not $__mul
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 71d5a5454..75b1242a2 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -93,7 +93,7 @@ module _80_mul (A, B, Y); .Y(Y)
);
`endif
- else if (A_WIDTH < B_WIDTH)
+ else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
\$mul #(
.A_SIGNED(B_SIGNED),
.B_SIGNED(A_SIGNED),
|