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| author | David Shah <dave@ds0.me> | 2019-08-30 13:57:15 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-30 13:57:15 +0100 |
| commit | 6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (patch) | |
| tree | 4780799b6c1dc1d150b80aa142e6c53e06760cb3 /techlibs/common | |
| parent | edff79a25a802e5b1816608b48e3ac335ad87147 (diff) | |
| parent | 694e30a35426b9582a1f2db730528d4d34305795 (diff) | |
| download | yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.gz yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.bz2 yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.zip | |
Merge branch 'master' into xc7dsp
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/synth.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 555de9fba..a176357a7 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass log_cmd_error("This command only operates on fully selected designs!\n"); if (abc == "abc9" && !lut) - log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)"); + log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n"); log_header(design, "Executing SYNTH pass.\n"); log_push(); |