Reformat so it shows up/looks nice when "help $alu" and "help $alu+"

1 files changed, 34 insertions, 25 deletions

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 1b172c112..7845a3fed 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -532,20 +532,24 @@ endmodule
 
 // --------------------------------------------------------
 
-// Lookahead carry unit
-//   A building block dedicated to fast computation of carry-bits
-//   used in binary arithmetic operations. By replacing the ripple
-//   carry structure used in full-adder blocks, the more significant
-//   bits of the sum can be expected to be computed more quickly.
-//   Typically created during `techmap` of $alu cells
-//   (see the "_90_alu" rule in +/techmap.v)
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $lcu (P, G, CI, CO)
+//-
+//- Lookahead carry unit
+//- A building block dedicated to fast computation of carry-bits used in binary
+//- arithmetic operations. By replacing the ripple carry structure used in full-adder
+//- blocks, the more significant  bits of the sum can be expected to be computed more
+//- quickly.
+//- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in
+//- +/techmap.v).
 module \$lcu (P, G, CI, CO);
 
 parameter WIDTH = 1;
 
-input [WIDTH-1:0] P;	// Propagate
-input [WIDTH-1:0] G;	// Generate
-input CI;		// Carry-in
+input [WIDTH-1:0] P;    // Propagate
+input [WIDTH-1:0] G;    // Generate
+input CI;               // Carry-in
 
 output reg [WIDTH-1:0] CO; // Carry-out
 
@@ -563,12 +567,17 @@ endmodule
 
 // --------------------------------------------------------
 
-// Arithmetic logic unit
-//   A building block supporting both binary addition/subtraction
-//   operations, and indirectly, comparison operations.
-//   Typically created by the `alumacc` pass, which transforms
-//   $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
-//   cells into this $alu cell.
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $alu (A, B, CI, BI, X, Y, CO)
+//-
+//- Arithmetic logic unit.
+//- A building block supporting both binary addition/subtraction operations, and
+//- indirectly, comparison operations.
+//- Typically created by the `alumacc` pass, which transforms:
+//-   $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
+//- cells into this $alu cell.
+//-
 module \$alu (A, B, CI, BI, X, Y, CO);
 
 parameter A_SIGNED = 0;
@@ -577,16 +586,16 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [A_WIDTH-1:0] A;		// Input operand
-input [B_WIDTH-1:0] B;		// Input operand
-output [Y_WIDTH-1:0] X;		// A xor B (sign-extended, optional B inversion,
-				//          used in combination with
-				//          reduction-AND for $eq/$ne ops)
-output [Y_WIDTH-1:0] Y;		// Sum
+input [A_WIDTH-1:0] A;      // Input operand
+input [B_WIDTH-1:0] B;      // Input operand
+output [Y_WIDTH-1:0] X;     // A xor B (sign-extended, optional B inversion,
+                            //          used in combination with
+                            //          reduction-AND for $eq/$ne ops)
+output [Y_WIDTH-1:0] Y;     // Sum
 
-input CI;			// Carry-in (set for $sub)
-input BI;			// Invert-B (set for $sub)
-output [Y_WIDTH-1:0] CO;	// Carry-out
+input CI;                   // Carry-in (set for $sub)
+input BI;                   // Invert-B (set for $sub)
+output [Y_WIDTH-1:0] CO;    // Carry-out
 
 wire [Y_WIDTH-1:0] AA, BB;