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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 10:11:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 10:11:36 -0700 |
| commit | ab46d9017b1a6fe6e376278ca9d3bec2e5673f06 (patch) | |
| tree | 861367cd4433de456c570bb27aea5d8de3b6e052 /techlibs/common | |
| parent | 70c5444b25f18760781509104f4393b3d0a05fc0 (diff) | |
| download | yosys-ab46d9017b1a6fe6e376278ca9d3bec2e5673f06.tar.gz yosys-ab46d9017b1a6fe6e376278ca9d3bec2e5673f06.tar.bz2 yosys-ab46d9017b1a6fe6e376278ca9d3bec2e5673f06.zip | |
Fix signedness bug
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index f2b44222e..3ca69b7b1 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -239,9 +239,9 @@ module _80_mul (A, B, Y); );
//assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
if (A_SIGNED && B_SIGNED)
- assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)];
- else
assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]);
+ else
+ assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)];
assign partial_sum[n][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
assign Y = partial_sum[n];
end
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