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| * Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-281-2/+17
* | Create +/abc9_model.v for $__ABC9_{DELAY,FF_}Eddie Hung2020-02-272-0/+11
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* techmap: fix shiftx2mux decompositionEddie Hung2020-02-071-8/+6
* shiftx2mux: fix select out of boundsEddie Hung2020-02-051-1/+2
* Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-052-2/+0
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| * abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-152-2/+0
* | Explicitly create separate $mux cellsEddie Hung2020-01-211-2/+2
* | Fix tests -- when Y_WIDTH is non-pow-2Eddie Hung2020-01-211-3/+4
* | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-213-73/+69
* | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-212-0/+39
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* Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
* Makefile: don't assume python is called `python3`Sean Cross2019-10-191-2/+2
* Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
* Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-34/+6
* mul2dsp.v slice namesEddie Hung2019-09-251-5/+5
* Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicitEddie Hung2019-09-251-3/+1
* Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"Eddie Hung2019-09-251-2/+6
* Revert "No need for $__mul anymore?"Eddie Hung2019-09-251-8/+8
* Remove _TECHMAP_CELLTYPE_ check since all $mulEddie Hung2019-09-251-6/+2
* No need for $__mul anymore?Eddie Hung2019-09-251-8/+8
* Fix signedness bugEddie Hung2019-09-201-2/+2
* Be sensitive to signednessEddie Hung2019-09-101-20/+21
* Really get rid of 'opt_expr -fine' by being explicitEddie Hung2019-09-101-6/+33
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-052-0/+2
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| * Use a dummy box file if none specifiedEddie Hung2019-08-282-0/+2
* | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-301-1/+1
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| * | Merge branch 'master' into xc7dspDavid Shah2019-08-301-1/+1
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| | * Missing newlineEddie Hung2019-08-201-1/+1
* | | Only swap ports if $mul and not $__mulEddie Hung2019-08-131-1/+1
* | | Add DSP_A_MAXWIDTH_PARTIAL, refactorEddie Hung2019-08-131-144/+110
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* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-121-8/+36
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| * Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
| * A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
| * Add more commentsEddie Hung2019-08-091-4/+18
| * Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-071-0/+19
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| * Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+19
* | Trim Y_WIDTHEddie Hung2019-08-011-5/+3
* | Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
* | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-011-4/+11
* | Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
* | Fix B_WIDTH > DSP_B_MAXWIDTH caseEddie Hung2019-08-011-32/+14
* | Do not compute sign bit if result is zeroEddie Hung2019-07-311-1/+2
* | For signed multipliers, compute sign bit separately...Eddie Hung2019-07-311-23/+42
* | Fix spacingEddie Hung2019-07-261-3/+3
* | Add copyright header, comment on cascadeEddie Hung2019-07-241-4/+34
* | Typo for Y_WIDTHEddie Hung2019-07-231-1/+1
* | Use minimum sized width wiresEddie Hung2019-07-221-7/+13
* | Indirection via $__soft_mulEddie Hung2019-07-191-9/+9
* | Do not do sign extension in techmap; let packer do itEddie Hung2019-07-191-14/+5