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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 16:41:09 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 16:41:09 -0800 |
| commit | 4c1d3a126d3978aeacbab623532c0ec9400b8959 (patch) | |
| tree | c195c2679a3292f73900011a059a706342a49e28 /techlibs/common | |
| parent | 505557e93e0263b7714bd37b274923a6369278f5 (diff) | |
| download | yosys-4c1d3a126d3978aeacbab623532c0ec9400b8959.tar.gz yosys-4c1d3a126d3978aeacbab623532c0ec9400b8959.tar.bz2 yosys-4c1d3a126d3978aeacbab623532c0ec9400b8959.zip | |
shiftx2mux: fix select out of bounds
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/techmap.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 75a51e55e..be6530eb4 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -152,10 +152,11 @@ module _90_shift_shiftx (A, B, Y); localparam len = 2**(B_WIDTH-1); localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH; wire [len-1:0] T, F, AA; + wire [(A_WIDTH+Y_WIDTH2*2):0] Apad = {{Y_WIDTH2*2{extbit}}, A}; genvar i; for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2]; - assign T[i/2 +: Y_WIDTH2] = (i + Y_WIDTH2 < A_WIDTH) ? A[i+Y_WIDTH2 +: Y_WIDTH2] : {Y_WIDTH2{extbit}}; + assign T[i/2 +: Y_WIDTH2] = Apad[i+Y_WIDTH2 +: Y_WIDTH2]; assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2]; end wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}; |