| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | techmap: Refactor to use FfInitVals. | Marcelina Kościelnicka | 2020-07-24 | 1 | -41/+4 |
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| * | techmap: Add _TECHMAP_CELLNAME_ special parameter. | Marcelina Kościelnicka | 2020-07-21 | 1 | -0/+6 |
| | | | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells. | ||||
| * | techmap: don't drop attributes on replaced cells. | whitequark | 2020-06-29 | 1 | -2/+3 |
| | | | | | | | This was introduced in 76c4ee4ea5cb6a3dc214f66237af22a1bedda010. Fixes #2204. | ||||
| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -2/+2 |
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| * | RTLIL: factor out RTLIL::Module::addMemory. NFC. | whitequark | 2020-06-04 | 1 | -7/+1 |
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| * | techmap, flatten: remove dead options. | whitequark | 2020-06-04 | 1 | -225/+168 |
| | | | | | | | After splitting the passes, some options can never be activated, and most conditions involving them become dead. Remove them, and also all of the newly dead code. | ||||
| * | flatten: split from techmap. | whitequark | 2020-06-03 | 1 | -93/+0 |
| | | | | | | | | Although the two passes started out very similar, they diverged over time and now have little in common. Moreover, `techmap` is extremely complex while `flatten` does not have to be, and this complexity interferes with improving `flatten`. | ||||
| * | techmap: remove dead variable. NFC. | whitequark | 2020-06-03 | 1 | -1/+0 |
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| * | techmap: use C++11 default member initializers. NFC. | whitequark | 2020-06-02 | 1 | -16/+6 |
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| * | techmap: simplify. | whitequark | 2020-06-02 | 1 | -7/+1 |
| | | | | | `rewrite_filename` is already called in `Frontend::extra_args`. | ||||
| * | techmap: use +/techmap.v instead of an ad-hoc code generator. | whitequark | 2020-06-02 | 1 | -3/+1 |
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| * | techmap: Replace naughty `const_cast<>()`s. | Alberto Gonzalez | 2020-05-14 | 1 | -2/+4 |
| | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | ||||
| * | techmap: Replace pseudo-private member usage with the range accessor ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -3/+3 |
| | | | | | function and some naughty `const_cast<>()`s. | ||||
| * | techmap: sort celltypeMap as it determines techmap order | Eddie Hung | 2020-05-14 | 1 | -1/+5 |
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| * | Replace `std::set`s using custom comparators with `pool`. | Alberto Gonzalez | 2020-05-14 | 1 | -4/+4 |
| | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | ||||
| * | techmap: prefix special wires with backslash for use as IdString | Eddie Hung | 2020-05-14 | 1 | -11/+12 |
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| * | Further clean up `passes/techmap/techmap.cc`. | Alberto Gonzalez | 2020-05-14 | 1 | -5/+6 |
| | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | ||||
| * | Use `emplace()` for more efficient insertion into various `dict`s. | Alberto Gonzalez | 2020-05-14 | 1 | -8/+8 |
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| * | Build constant bits directly rather than constructing an object and copying ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -2/+5 |
| | | | | | its bits. | ||||
| * | Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`. | Alberto Gonzalez | 2020-05-14 | 1 | -2/+2 |
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| * | Use `emplace()` rather than `insert()`. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+1 |
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| * | Clean up pseudo-private member usage and ensure range iteration uses ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -17/+17 |
| | | | | | references where possible to avoid unnecessary copies. | ||||
| * | Clean up extraneous buffer. | Alberto Gonzalez | 2020-05-14 | 1 | -5/+2 |
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| * | Replace `std::map` with `dict` for `unique_bit_id`. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+1 |
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| * | Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -3/+3 |
| | | | | | `cellbits_to_tplbits`. | ||||
| * | Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -3/+3 |
| | | | | | `outbit_to_cell`. | ||||
| * | Replace `std::map` with `dict` for `TechmapWires` type. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+1 |
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| * | Replace `std::map` with `dict` for `celltypeMap`. | Alberto Gonzalez | 2020-05-14 | 1 | -3/+3 |
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| * | Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`. | Alberto Gonzalez | 2020-05-14 | 1 | -4/+4 |
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| * | Replace `std::map` with `dict` for `positional_ports`. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+1 |
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| * | Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -4/+4 |
| | | | | | `std::map` for `techmap_cache` and `techmap_do_cache`. | ||||
| * | Replace `std::map` with `dict` for `simplemap_mappers`. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+1 |
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| * | Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`. | Alberto Gonzalez | 2020-05-14 | 1 | -10/+10 |
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| * | Replace `std::string` and `RTLIL::IdString` with `IdString` in ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -21/+21 |
| | | | | | | | `passes/techmap/techmap.cc`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | ||||
| * | Do not modify design modules while iterating over `modules()`. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+4 |
| | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | ||||
| * | Clean up pseudo-private member usage, superfluous `std::vector` ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -76/+70 |
| | | | | | instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`. | ||||
| * | techmap: fix error message | Eddie Hung | 2020-04-14 | 1 | -1/+1 |
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| * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -40/+40 |
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| * | Merge pull request #1845 from YosysHQ/eddie/kernel_speedup | Eddie Hung | 2020-04-02 | 1 | -2/+2 |
| |\ | | | | | kernel: speedup by using more pass-by-const-ref | ||||
| | * | kernel: SigSpec use more const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-13 | 1 | -2/+2 |
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| * | | techmap: Fix cell names with _TECHMAP_REPLACE_.* | Marcin Kościelnicki | 2020-03-23 | 1 | -1/+1 |
| |/ | | | | Fixes #1804. | ||||
| * | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf | Eddie Hung | 2019-10-02 | 1 | -4/+8 |
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| * | techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias | Eddie Hung | 2019-09-30 | 1 | -0/+10 |
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| * | Fix _TECHMAP_REMOVEINIT_ handling. | Marcin Kościelnicki | 2019-09-27 | 1 | -13/+17 |
| | | | | | | | | | Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396. | ||||
| * | Trim mismatched connection to be same (smallest) size | Eddie Hung | 2019-09-20 | 1 | -0/+6 |
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| * | Fix first testcase in #1391 | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
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| * | Add techmap_autopurge attribute, fixes #1381 | Clifford Wolf | 2019-09-19 | 1 | -5/+49 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | techmap: Add support for extracting init values of ports | Marcin Kościelnicki | 2019-09-07 | 1 | -1/+70 |
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| * | Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes ↵ | Clifford Wolf | 2019-09-05 | 1 | -8/+24 |
| | | | | | | | #1220 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add flatten handling of pre-existing wires as created by interfaces, fixes #1145 | Clifford Wolf | 2019-09-05 | 1 | -8/+20 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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index : iCE40/yosys | |
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