flatten: split from techmap.

Although the two passes started out very similar, they diverged over
time and now have little in common. Moreover, `techmap` is extremely
complex while `flatten` does not have to be, and this complexity
interferes with improving `flatten`.

1 files changed, 0 insertions, 93 deletions

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index c88f7bd0a..8659d0f36 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1333,97 +1333,4 @@ struct TechmapPass : public Pass {
 	}
 } TechmapPass;
 
-struct FlattenPass : public Pass {
-	FlattenPass() : Pass("flatten", "flatten design") { }
-	void help() YS_OVERRIDE
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("    flatten [options] [selection]\n");
-		log("\n");
-		log("This pass flattens the design by replacing cells by their implementation. This\n");
-		log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
-		log("pass is using the current design as mapping library.\n");
-		log("\n");
-		log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
-		log("flattened by this command.\n");
-		log("\n");
-		log("    -wb\n");
-		log("        Ignore the 'whitebox' attribute on cell implementations.\n");
-		log("\n");
-	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-	{
-		log_header(design, "Executing FLATTEN pass (flatten design).\n");
-		log_push();
-
-		TechmapWorker worker;
-		worker.flatten_mode = true;
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			if (args[argidx] == "-wb") {
-				worker.ignore_wb = true;
-				continue;
-			}
-			break;
-		}
-		extra_args(args, argidx, design);
-
-
-		dict<IdString, pool<IdString>> celltypeMap;
-		for (auto module : design->modules())
-			celltypeMap[module->name].insert(module->name);
-		for (auto &i : celltypeMap)
-			i.second.sort(RTLIL::sort_by_id_str());
-
-		RTLIL::Module *top_mod = nullptr;
-		if (design->full_selection())
-			for (auto mod : design->modules())
-				if (mod->get_bool_attribute(ID::top))
-					top_mod = mod;
-
-		pool<RTLIL::Cell*> handled_cells;
-		if (top_mod != nullptr) {
-			worker.flatten_do_list.insert(top_mod->name);
-			while (!worker.flatten_do_list.empty()) {
-				auto mod = design->module(*worker.flatten_do_list.begin());
-				while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
-				worker.flatten_done_list.insert(mod->name);
-				worker.flatten_do_list.erase(mod->name);
-			}
-		} else {
-			for (auto mod : design->modules().to_vector())
-				while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
-		}
-
-		log_suppressed();
-		log("No more expansions possible.\n");
-
-		if (top_mod != nullptr)
-		{
-			pool<IdString> used_modules, new_used_modules;
-			new_used_modules.insert(top_mod->name);
-			while (!new_used_modules.empty()) {
-				pool<IdString> queue;
-				queue.swap(new_used_modules);
-				for (auto modname : queue)
-					used_modules.insert(modname);
-				for (auto modname : queue)
-					for (auto cell : design->module(modname)->cells())
-						if (design->module(cell->type) && !used_modules[cell->type])
-							new_used_modules.insert(cell->type);
-			}
-
-			for (auto mod : design->modules().to_vector())
-				if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) {
-					log("Deleting now unused module %s.\n", log_id(mod));
-					design->remove(mod);
-				}
-		}
-
-		log_pop();
-	}
-} FlattenPass;
-
 PRIVATE_NAMESPACE_END