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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-19 22:24:20 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-14 20:06:53 +0000 |
| commit | 67f4046c05622140d9d2ae93d8cc44bb680b3b20 (patch) | |
| tree | d44b4d4673944954987e875be017aa2233900aac /passes/techmap/techmap.cc | |
| parent | 64c16f8c1364bbe45bc17a54c29d70990efb45ad (diff) | |
| download | yosys-67f4046c05622140d9d2ae93d8cc44bb680b3b20.tar.gz yosys-67f4046c05622140d9d2ae93d8cc44bb680b3b20.tar.bz2 yosys-67f4046c05622140d9d2ae93d8cc44bb680b3b20.zip | |
Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.
Diffstat (limited to 'passes/techmap/techmap.cc')
| -rw-r--r-- | passes/techmap/techmap.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 651f772c9..55d80bad1 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -463,7 +463,7 @@ struct TechmapWorker } } - bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells, + bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells, const std::map<IdString, std::set<IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion) { std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; @@ -805,7 +805,7 @@ struct TechmapWorker bool keep_running = true; techmap_do_cache[tpl] = true; - std::set<IdString> techmap_wire_names; + pool<IdString> techmap_wire_names; while (keep_running) { @@ -1324,7 +1324,7 @@ struct TechmapPass : public Pass { int module_max_iter = max_iter; bool did_something = true; - std::set<RTLIL::Cell*> handled_cells; + pool<RTLIL::Cell*> handled_cells; while (did_something) { did_something = false; if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false)) @@ -1391,7 +1391,7 @@ struct FlattenPass : public Pass { if (mod->get_bool_attribute(ID::top)) top_mod = mod; - std::set<RTLIL::Cell*> handled_cells; + pool<RTLIL::Cell*> handled_cells; if (top_mod != nullptr) { worker.flatten_do_list.insert(top_mod->name); while (!worker.flatten_do_list.empty()) { |