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authorAlberto Gonzalez <boqwxp@airmail.cc>2020-04-10 07:19:05 +0000
committerAlberto Gonzalez <boqwxp@airmail.cc>2020-05-14 20:06:53 +0000
commite49fdee40441cb4b1892007560d56467fd75a798 (patch)
tree40f7a1bb895883f539e55c168caa3d68a579c961 /passes/techmap/techmap.cc
parent985a29ff3b1f9ce19b091aa2541dc07dbc669341 (diff)
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Do not modify design modules while iterating over `modules()`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
Diffstat (limited to 'passes/techmap/techmap.cc')
-rw-r--r--passes/techmap/techmap.cc5
1 files changed, 4 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index f300c2f72..930b4c416 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1423,11 +1423,14 @@ struct FlattenPass : public Pass {
new_used_modules.insert(cell->type);
}
+ std::set<RTLIL::Module *> to_remove;
for (auto mod : design->modules())
if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) {
log("Deleting now unused module %s.\n", log_id(mod));
- design->remove(mod);
+ to_remove.insert(mod);
}
+ for (auto mod : to_remove)
+ design->remove(mod);
}
log_pop();