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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-13 08:17:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-13 08:17:39 -0700 |
| commit | 432a09af80f7dcba9fd517a001e3a1954c99537e (patch) | |
| tree | 1adf4d0a7cdf929de445b000255dfa8ca23663a5 /passes/techmap/techmap.cc | |
| parent | b567f03c266b0c44d81a24dde2ed538f1db05d4e (diff) | |
| download | yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.tar.gz yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.tar.bz2 yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.zip | |
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
Diffstat (limited to 'passes/techmap/techmap.cc')
| -rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 0c57733d4..5ddc18a12 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -906,8 +906,8 @@ struct TechmapWorker RTLIL::SigSig port_conn; for (auto &it : port_connmap) { - port_conn.first.append_bit(it.first); - port_conn.second.append_bit(it.second); + port_conn.first.append(it.first); + port_conn.second.append(it.second); } tpl->connect(port_conn); |