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| author | whitequark <whitequark@whitequark.org> | 2020-06-02 22:19:34 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-02 23:43:20 +0000 |
| commit | 68d747f76769ce6e517cc72263ccc89ef5dff43f (patch) | |
| tree | 78a9ca1e2c199908971f9bfa2070a8d3365a1d0c /passes/techmap/techmap.cc | |
| parent | 4b3f48a7ec5d00395f50d46ed0222c01dee9fc09 (diff) | |
| download | yosys-68d747f76769ce6e517cc72263ccc89ef5dff43f.tar.gz yosys-68d747f76769ce6e517cc72263ccc89ef5dff43f.tar.bz2 yosys-68d747f76769ce6e517cc72263ccc89ef5dff43f.zip | |
techmap: use +/techmap.v instead of an ad-hoc code generator.
Diffstat (limited to 'passes/techmap/techmap.cc')
| -rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 6ac1d1113..fc24c33b0 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -27,7 +27,6 @@ #include <string.h> #include "simplemap.h" -#include "passes/techmap/techmap.inc" YOSYS_NAMESPACE_BEGIN @@ -1282,8 +1281,7 @@ struct TechmapPass : public Pass { RTLIL::Design *map = new RTLIL::Design; if (map_files.empty()) { - std::istringstream f(stdcells_code); - Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend); + Frontend::frontend_call(map, nullptr, "+/techmap.v", verilog_frontend); } else { for (auto &fn : map_files) if (fn.compare(0, 1, "%") == 0) { |