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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-27 00:55:43 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-09-05 13:30:58 +0200 |
| commit | 694a8f75cf7a8bcf86a421ca6c9fe3560b1e2a0f (patch) | |
| tree | c077dcccb3c6e658a64294b06ee9209aab114d51 /passes/techmap/techmap.cc | |
| parent | 8d9196066370b156ae2beefed5aa2da545255e4c (diff) | |
| download | yosys-694a8f75cf7a8bcf86a421ca6c9fe3560b1e2a0f.tar.gz yosys-694a8f75cf7a8bcf86a421ca6c9fe3560b1e2a0f.tar.bz2 yosys-694a8f75cf7a8bcf86a421ca6c9fe3560b1e2a0f.zip | |
Add flatten handling of pre-existing wires as created by interfaces, fixes #1145
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/techmap/techmap.cc')
| -rw-r--r-- | passes/techmap/techmap.cc | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c4496f76f..cb01cadb1 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -211,14 +211,26 @@ struct TechmapWorker positional_ports[stringf("$%d", it.second->port_id)] = it.first; IdString w_name = it.second->name; apply_prefix(cell->name, w_name); - RTLIL::Wire *w = module->addWire(w_name, it.second); - w->port_input = false; - w->port_output = false; - w->port_id = 0; - if (it.second->get_bool_attribute(ID(_techmap_special_))) - w->attributes.clear(); - if (w->attributes.count(ID(src))) - w->add_strpool_attribute(ID(src), extra_src_attrs); + RTLIL::Wire *w = module->wire(w_name); + if (w != nullptr) { + if (!flatten_mode) + log_error("Signal %s.%s conflicts with %s.%s (via %s.%s).\n", log_id(module), log_id(w), + log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); + if (GetSize(w) < GetSize(it.second)) { + log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), + log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); + w->width = GetSize(it.second); + } + } else { + w = module->addWire(w_name, it.second); + w->port_input = false; + w->port_output = false; + w->port_id = 0; + if (it.second->get_bool_attribute(ID(_techmap_special_))) + w->attributes.clear(); + if (w->attributes.count(ID(src))) + w->add_strpool_attribute(ID(src), extra_src_attrs); + } design->select(module, w); } |