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* Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmapwhitequark2020-08-271-5/+3
|\ | | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap
| * flatten, techmap: don't canonicalize tpl driven bits via sigmap.whitequark2020-08-261-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For connection `assign a = b;`, `sigmap(a)` returns `b`. This is exactly the opposite of the desired canonicalization for driven bits. Consider the following code: module foo(inout a, b); assign a = b; endmodule module bar(output c); foo f(c, 1'b0); endmodule Before this commit, the inout ports would be swapped after flattening (and cause a crash while attempting to drive a constant value). This issue was introduced in 9f772eb9. Fixes #2183.
* | Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-2/+2
|/ | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fixclairexen2020-08-201-1/+22
|\ | | | | techmap.CONSTMAP: Handle outputs before inputs.
| * techmap.CONSTMAP: Handle outputs before inputs.Marcelina Kościelnicka2020-08-051-1/+22
| | | | | | | | Fixes #2321.
* | techmap: Add support for [] wildcards in techmap_celltype.Marcelina Kościelnicka2020-08-021-4/+32
|/ | | | Fixes #1826.
* techmap: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-41/+4
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* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-0/+6
| | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* techmap: don't drop attributes on replaced cells.whitequark2020-06-291-2/+3
| | | | | | This was introduced in 76c4ee4ea5cb6a3dc214f66237af22a1bedda010. Fixes #2204.
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-041-7/+1
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* techmap, flatten: remove dead options.whitequark2020-06-041-225/+168
| | | | | | After splitting the passes, some options can never be activated, and most conditions involving them become dead. Remove them, and also all of the newly dead code.
* flatten: split from techmap.whitequark2020-06-031-93/+0
| | | | | | | Although the two passes started out very similar, they diverged over time and now have little in common. Moreover, `techmap` is extremely complex while `flatten` does not have to be, and this complexity interferes with improving `flatten`.
* techmap: remove dead variable. NFC.whitequark2020-06-031-1/+0
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* techmap: use C++11 default member initializers. NFC.whitequark2020-06-021-16/+6
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* techmap: simplify.whitequark2020-06-021-7/+1
| | | | `rewrite_filename` is already called in `Frontend::extra_args`.
* techmap: use +/techmap.v instead of an ad-hoc code generator.whitequark2020-06-021-3/+1
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* techmap: Replace naughty `const_cast<>()`s.Alberto Gonzalez2020-05-141-2/+4
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* techmap: Replace pseudo-private member usage with the range accessor ↵Alberto Gonzalez2020-05-141-3/+3
| | | | function and some naughty `const_cast<>()`s.
* techmap: sort celltypeMap as it determines techmap orderEddie Hung2020-05-141-1/+5
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* Replace `std::set`s using custom comparators with `pool`.Alberto Gonzalez2020-05-141-4/+4
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* techmap: prefix special wires with backslash for use as IdStringEddie Hung2020-05-141-11/+12
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* Further clean up `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-5/+6
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Use `emplace()` for more efficient insertion into various `dict`s.Alberto Gonzalez2020-05-141-8/+8
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* Build constant bits directly rather than constructing an object and copying ↵Alberto Gonzalez2020-05-141-2/+5
| | | | its bits.
* Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.Alberto Gonzalez2020-05-141-2/+2
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* Use `emplace()` rather than `insert()`.Alberto Gonzalez2020-05-141-1/+1
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* Clean up pseudo-private member usage and ensure range iteration uses ↵Alberto Gonzalez2020-05-141-17/+17
| | | | references where possible to avoid unnecessary copies.
* Clean up extraneous buffer.Alberto Gonzalez2020-05-141-5/+2
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* Replace `std::map` with `dict` for `unique_bit_id`.Alberto Gonzalez2020-05-141-1/+1
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* Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | `cellbits_to_tplbits`.
* Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | `outbit_to_cell`.
* Replace `std::map` with `dict` for `TechmapWires` type.Alberto Gonzalez2020-05-141-1/+1
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* Replace `std::map` with `dict` for `celltypeMap`.Alberto Gonzalez2020-05-141-3/+3
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* Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.Alberto Gonzalez2020-05-141-4/+4
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* Replace `std::map` with `dict` for `positional_ports`.Alberto Gonzalez2020-05-141-1/+1
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* Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵Alberto Gonzalez2020-05-141-4/+4
| | | | `std::map` for `techmap_cache` and `techmap_do_cache`.
* Replace `std::map` with `dict` for `simplemap_mappers`.Alberto Gonzalez2020-05-141-1/+1
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* Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-10/+10
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* Replace `std::string` and `RTLIL::IdString` with `IdString` in ↵Alberto Gonzalez2020-05-141-21/+21
| | | | | | `passes/techmap/techmap.cc`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Do not modify design modules while iterating over `modules()`.Alberto Gonzalez2020-05-141-1/+4
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Clean up pseudo-private member usage, superfluous `std::vector` ↵Alberto Gonzalez2020-05-141-76/+70
| | | | instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
* techmap: fix error messageEddie Hung2020-04-141-1/+1
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-40/+40
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-2/+2
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-131-2/+2
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* | techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-231-1/+1
|/ | | | Fixes #1804.
* Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
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* techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-13/+17
| | | | | | | | Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396.
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