| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 10 | -33/+33 |
| * | Added $eq/$neq -> $logic_not/$reduce_bool optimization | Clifford Wolf | 2015-04-29 | 1 | -1/+3 |
| * | Added onehot attribute | Clifford Wolf | 2015-02-04 | 1 | -0/+3 |
| * | Added "fsm -encfile" | Clifford Wolf | 2015-01-30 | 2 | -12/+41 |
| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -2/+2 |
| * | Renamed extend() to extend_xx(), changed most users to extend_u0() | Clifford Wolf | 2014-12-24 | 1 | -1/+1 |
| * | Added log_warning() API | Clifford Wolf | 2014-11-09 | 1 | -1/+1 |
| * | Changed from "and" to "&&" | William Speirs | 2014-10-15 | 1 | -1/+1 |
| * | Do not the 'z' modifier in format string (another win32 fix) | Clifford Wolf | 2014-10-11 | 2 | -4/+4 |
| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 5 | -20/+20 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 10 | -3/+47 |
| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -1/+1 |
| * | Don't change existing binary FSM encoding if it is already optimal | Clifford Wolf | 2014-08-30 | 1 | -1/+6 |
| * | Using $pmux info in fsm_extract to optimize transition ctrl_in patterns | Clifford Wolf | 2014-08-30 | 1 | -0/+10 |
| * | Improved handling of $pmux cells in fsm_extract | Clifford Wolf | 2014-08-30 | 1 | -20/+75 |
| * | Added module->uniquify() | Clifford Wolf | 2014-08-16 | 1 | -5/+1 |
| * | More idstring sort_by_* helpers and fixed tpl ordering in techmap | Clifford Wolf | 2014-08-15 | 1 | -4/+4 |
| * | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 3 | -3/+3 |
| * | Some improvements in FSM mapping and recoding | Clifford Wolf | 2014-08-14 | 2 | -8/+16 |
| * | Fixed FSM mapping for multiple reset-like signals | Clifford Wolf | 2014-08-10 | 1 | -1/+21 |
| * | Some improvements in fsm_opt and fsm_map for FSM with unreachable states | Clifford Wolf | 2014-08-09 | 2 | -50/+101 |
| * | Another fsm_extract bugfix | Clifford Wolf | 2014-08-08 | 1 | -0/+4 |
| * | Fixed "fsm -export" | Clifford Wolf | 2014-08-08 | 2 | -6/+5 |
| * | Fixed fsm_extract for wreduced muxes | Clifford Wolf | 2014-08-08 | 1 | -8/+25 |
| * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 3 | -4/+4 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 6 | -84/+84 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -2/+2 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 2 | -4/+4 |
| * | Added log_cmd_error_expection | Clifford Wolf | 2014-07-27 | 1 | -4/+1 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 8 | -8/+8 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 8 | -13/+13 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 2 | -5/+5 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 2 | -19/+6 |
| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 3 | -10/+10 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 3 | -9/+17 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 6 | -94/+94 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 6 | -94/+94 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 3 | -60/+19 |
| * | Various small fixes (from gcc compiler warnings) | Clifford Wolf | 2014-07-23 | 1 | -4/+4 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -5/+0 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -8/+8 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 1 | -8/+8 |
| * | SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands | Clifford Wolf | 2014-07-22 | 3 | -38/+19 |
| * | fixed memory leak in fsm_opt | Clifford Wolf | 2014-07-22 | 1 | -1/+3 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 1 | -2/+2 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 6 | -58/+58 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 6 | -58/+58 |
| * | Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys | Clifford Wolf | 2014-03-11 | 1 | -1/+2 |
| * | Fixes in fsm detect/extract for better detection of non-fsm circuits | Clifford Wolf | 2013-12-06 | 2 | -4/+4 |
