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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-14 11:39:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-14 11:39:46 +0200 |
| commit | 13f2f36884fa3e4a8329dab2556af7000cb085df (patch) | |
| tree | 59787125c75220ee6f78d160e6cc6cfcc583d0ec /passes/fsm | |
| parent | 28cf48e31f049f8343023de46cd916ac47fcfc5d (diff) | |
| download | yosys-13f2f36884fa3e4a8329dab2556af7000cb085df.tar.gz yosys-13f2f36884fa3e4a8329dab2556af7000cb085df.tar.bz2 yosys-13f2f36884fa3e4a8329dab2556af7000cb085df.zip | |
RIP $safe_pmux
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 5675dff50..2c846a4cf 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -50,7 +50,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig std::set<sig2driver_entry_t> cellport_list; sig2driver.find(sig, cellport_list); for (auto &cellport : cellport_list) { - if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y") + if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y") return false; RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A")); RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B")); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 670fae1d9..77821326d 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -42,7 +42,7 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") + if (cell->type == "$mux" || cell->type == "$pmux") if (cell->getPort("\\A").size() < 2) return true; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index ebe3073de..871478dee 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -55,7 +55,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); - if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") { + if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != "\\Y") { log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; } |