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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-29 07:28:15 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-29 07:28:15 +0200 |
| commit | f483dce7c231f83937b5944ed0166a70594a0e8b (patch) | |
| tree | f9a2dc487da84ba9fcd53d8c56991b1dbe2dd7de /passes/fsm | |
| parent | 9d067fecea8d17dc3e800d09973f5ddaae41774b (diff) | |
| download | yosys-f483dce7c231f83937b5944ed0166a70594a0e8b.tar.gz yosys-f483dce7c231f83937b5944ed0166a70594a0e8b.tar.bz2 yosys-f483dce7c231f83937b5944ed0166a70594a0e8b.zip | |
Added $eq/$neq -> $logic_not/$reduce_bool optimization
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 68667ef02..b5250970b 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -305,7 +305,9 @@ static void extract_fsm(RTLIL::Wire *wire) for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); - RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); + RTLIL::SigSpec sig_b; + if (cell->hasPort("\\B")) + sig_b = assign_map(cell->getPort("\\B")); RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y")); if (cellport.second == "\\A" && !sig_b.is_fully_const()) continue; |