SigSpec refactoring: using the accessor functions everywhere

6 files changed, 58 insertions, 58 deletions

diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 523feae92..2ba4c72b8 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -56,8 +56,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
 		RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]);
 		if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor))
 			return false;
-		for (int i = 0; i < sig_b.__width; i += sig_a.__width)
-			if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.__width), recursion_monitor))
+		for (int i = 0; i < sig_b.size(); i += sig_a.size())
+			if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.size()), recursion_monitor))
 				return false;
 		muxtree_cells.insert(cellport.first);
 	}
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index e4d20077c..0dd328db3 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -43,7 +43,7 @@ struct FsmExpand
 	bool is_cell_merge_candidate(RTLIL::Cell *cell)
 	{
 		if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
-			if (cell->connections.at("\\A").__width < 2)
+			if (cell->connections.at("\\A").size() < 2)
 				return true;
 
 		RTLIL::SigSpec new_signals;
@@ -62,7 +62,7 @@ struct FsmExpand
 		new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"]));
 		new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"]));
 
-		if (new_signals.__width > 3)
+		if (new_signals.size() > 3)
 			return false;
 
 		if (cell->connections.count("\\Y") > 0) {
@@ -73,7 +73,7 @@ struct FsmExpand
 			new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"]));
 		}
 
-		if (new_signals.__width > 2)
+		if (new_signals.size() > 2)
 			return false;
 
 		return true;
@@ -145,8 +145,8 @@ struct FsmExpand
 
 		std::vector<RTLIL::Const> truth_tab;
 
-		for (int i = 0; i < (1 << input_sig.__width); i++) {
-			RTLIL::Const in_val(i, input_sig.__width);
+		for (int i = 0; i < (1 << input_sig.size()); i++) {
+			RTLIL::Const in_val(i, input_sig.size());
 			RTLIL::SigSpec A, B, S;
 			if (cell->connections.count("\\A") > 0)
 				A = assign_map(cell->connections["\\A"]);
@@ -166,17 +166,17 @@ struct FsmExpand
 		FsmData fsm_data;
 		fsm_data.copy_from_cell(fsm_cell);
 
-		fsm_data.num_inputs += input_sig.__width;
+		fsm_data.num_inputs += input_sig.size();
 		fsm_cell->connections["\\CTRL_IN"].append(input_sig);
 
-		fsm_data.num_outputs += output_sig.__width;
+		fsm_data.num_outputs += output_sig.size();
 		fsm_cell->connections["\\CTRL_OUT"].append(output_sig);
 
 		std::vector<FsmData::transition_t> new_transition_table;
 		for (auto &tr : fsm_data.transition_table) {
-			for (int i = 0; i < (1 << input_sig.__width); i++) {
+			for (int i = 0; i < (1 << input_sig.size()); i++) {
 				FsmData::transition_t new_tr = tr;
-				RTLIL::Const in_val(i, input_sig.__width);
+				RTLIL::Const in_val(i, input_sig.size());
 				RTLIL::Const out_val = truth_tab[i];
 				RTLIL::SigSpec ctrl_in = new_tr.ctrl_in;
 				RTLIL::SigSpec ctrl_out = new_tr.ctrl_out;
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index c0b5857f0..701b09bd8 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -36,7 +36,7 @@ static SigSet<sig2driver_entry_t> sig2driver, sig2trigger;
 
 static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL)
 {
-	sig.extend(dff_out.__width, false);
+	sig.extend(dff_out.size(), false);
 
 	if (sig == dff_out)
 		return true;
@@ -44,10 +44,10 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 	assign_map.apply(sig);
 	if (sig.is_fully_const()) {
 		sig.optimize();
-		assert(sig.__chunks.size() == 1);
-		if (states.count(sig.__chunks[0].data) == 0) {
+		assert(sig.chunks().size() == 1);
+		if (states.count(sig.chunks()[0].data) == 0) {
 			log("  found state code: %s\n", log_signal(sig));
-			states[sig.__chunks[0].data] = -1;
+			states[sig.chunks()[0].data] = -1;
 		}
 		return true;
 	}
@@ -73,14 +73,14 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 					break;
 				log("  found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state));
 			} while (0);
-		if (ctrl.extract(sig_s).__width == 0) {
+		if (ctrl.extract(sig_s).size() == 0) {
 			log("  found ctrl input: %s\n", log_signal(sig_s));
 			ctrl.append(sig_s);
 		}
 		if (!find_states(sig_a, dff_out, ctrl, states))
 			return false;
-		for (int i = 0; i < sig_b.__width/sig_a.__width; i++) {
-			if (!find_states(sig_b.extract(i*sig_a.__width, sig_a.__width), dff_out, ctrl, states))
+		for (int i = 0; i < sig_b.size()/sig_a.size(); i++) {
+			if (!find_states(sig_b.extract(i*sig_a.size(), sig_a.size()), dff_out, ctrl, states))
 				return false;
 		}
 	}
@@ -90,11 +90,11 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 
 static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec())
 {
-	if (dont_care.__width > 0) {
+	if (dont_care.size() > 0) {
 		sig.expand();
-		for (auto &chunk : sig.__chunks) {
+		for (auto &chunk : sig.chunks()) {
 			assert(chunk.width == 1);
-			if (dont_care.extract(chunk).__width > 0)
+			if (dont_care.extract(chunk).size() > 0)
 				chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
 		}
 		sig.optimize();
@@ -104,17 +104,17 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
 	ce.values_map.apply(sig);
 
 	sig.expand();
-	for (auto &chunk : sig.__chunks) {
+	for (auto &chunk : sig.chunks()) {
 		assert(chunk.width == 1);
 		if (chunk.wire != NULL)
 			chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
 	}
 	sig.optimize();
 
-	if (sig.__width == 0)
+	if (sig.size() == 0)
 		return RTLIL::Const();
-	assert(sig.__chunks.size() == 1 && sig.__chunks[0].wire == NULL);
-	return sig.__chunks[0].data;
+	assert(sig.chunks().size() == 1 && sig.chunks()[0].wire == NULL);
+	return sig.chunks()[0].data;
 }
 
 static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_data, std::map<RTLIL::Const, int> &states, int state_in, RTLIL::SigSpec ctrl_in, RTLIL::SigSpec ctrl_out, RTLIL::SigSpec dff_in, RTLIL::SigSpec dont_care)
@@ -144,7 +144,7 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d
 		return;
 	}
 
-	log_assert(undef.__width > 0);
+	log_assert(undef.size() > 0);
 	log_assert(ce.stop_signals.check_all(undef));
 
 	undef = undef.extract(0, 1);
@@ -258,8 +258,8 @@ static void extract_fsm(RTLIL::Wire *wire)
 	// Initialize fsm data struct
 
 	FsmData fsm_data;
-	fsm_data.num_inputs = ctrl_in.__width;
-	fsm_data.num_outputs = ctrl_out.__width;
+	fsm_data.num_inputs = ctrl_in.size();
+	fsm_data.num_outputs = ctrl_out.size();
 	fsm_data.state_bits = wire->width;
 	fsm_data.reset_state = -1;
 	for (auto &it : states) {
@@ -314,7 +314,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 		RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
 		RTLIL::Wire *unconn_wire = new RTLIL::Wire;
 		unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
-		unconn_wire->width = unconn_sig.__width;
+		unconn_wire->width = unconn_sig.size();
 		module->wires[unconn_wire->name] = unconn_wire;
 		port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections[cellport.second]);
 	}
@@ -367,7 +367,7 @@ struct FsmExtractPass : public Pass {
 						sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
 					}
 					if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections.count("\\Y") > 0 &&
-							cell_it.second->connections["\\Y"].__width == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
+							cell_it.second->connections["\\Y"].size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);
 						sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index f11d78b39..f8ffee523 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -50,12 +50,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				or_sig.append(RTLIL::SigSpec(state_onehot, 1, in_state));
 		or_sig.optimize();
 
-		if (or_sig.__width == 0)
+		if (or_sig.size() == 0)
 			continue;
 
 		RTLIL::SigSpec and_sig;
 
-		if (eq_sig_a.__width > 0)
+		if (eq_sig_a.size() > 0)
 		{
 			RTLIL::Wire *eq_wire = new RTLIL::Wire;
 			eq_wire->name = NEW_ID;
@@ -69,17 +69,17 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 			eq_cell->connections["\\Y"] = RTLIL::SigSpec(eq_wire);
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
-			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.__width);
-			eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.__width);
+			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
+			eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size());
 			eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 			module->add(eq_cell);
 
 			and_sig.append(RTLIL::SigSpec(eq_wire));
 		}
 
-		if (or_sig.__width < num_states-int(fullstate_cache.size()))
+		if (or_sig.size() < num_states-int(fullstate_cache.size()))
 		{
-			if (or_sig.__width == 1)
+			if (or_sig.size() == 1)
 			{
 				and_sig.append(or_sig);
 			}
@@ -95,7 +95,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				or_cell->connections["\\A"] = or_sig;
 				or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire);
 				or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
-				or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.__width);
+				or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
 				or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 				module->add(or_cell);
 
@@ -103,7 +103,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 			}
 		}
 
-		switch (and_sig.__width)
+		switch (and_sig.size())
 		{
 		case 2:
 			{
@@ -138,17 +138,17 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 		}
 	}
 
-	if (cases_vector.__width > 1) {
+	if (cases_vector.size() > 1) {
 		RTLIL::Cell *or_cell = new RTLIL::Cell;
 		or_cell->name = NEW_ID;
 		or_cell->type = "$reduce_or";
 		or_cell->connections["\\A"] = cases_vector;
 		or_cell->connections["\\Y"] = output;
 		or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
-		or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.__width);
+		or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
 		or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 		module->add(or_cell);
-	} else if (cases_vector.__width == 1) {
+	} else if (cases_vector.size() == 1) {
 		module->connections.push_back(RTLIL::SigSig(output, cases_vector));
 	} else {
 		module->connections.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1)));
@@ -237,8 +237,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 			eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i);
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
-			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.__width);
-			eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.__width);
+			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
+			eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size());
 			eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 			module->add(eq_cell);
 		}
@@ -308,8 +308,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		mux_cell->connections["\\B"] = sig_b;
 		mux_cell->connections["\\S"] = sig_s;
 		mux_cell->connections["\\Y"] = RTLIL::SigSpec(next_state_wire);
-		mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.__width);
-		mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.__width);
+		mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
+		mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
 		module->add(mux_cell);
 	}
 
diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index 6732d2abd..367b38eb1 100644
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -33,11 +33,11 @@ struct FsmOpt
 	
 	bool signal_is_unused(RTLIL::SigSpec sig)
 	{
-		assert(sig.__width == 1);
+		assert(sig.size() == 1);
 		sig.optimize();
 
-		RTLIL::Wire *wire = sig.__chunks[0].wire;
-		int bit = sig.__chunks[0].offset;
+		RTLIL::Wire *wire = sig.chunks()[0].wire;
+		int bit = sig.chunks()[0].offset;
 
 		if (!wire || wire->attributes.count("\\unused_bits") == 0)
 			return false;
@@ -55,11 +55,11 @@ struct FsmOpt
 	void opt_const_and_unused_inputs()
 	{
 		RTLIL::SigSpec ctrl_in = cell->connections["\\CTRL_IN"];
-		std::vector<bool> ctrl_in_used(ctrl_in.__width);
+		std::vector<bool> ctrl_in_used(ctrl_in.size());
 
 		std::vector<FsmData::transition_t> new_transition_table;
 		for (auto &tr : fsm_data.transition_table) {
-			for (int i = 0; i < ctrl_in.__width; i++) {
+			for (int i = 0; i < ctrl_in.size(); i++) {
 				RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1);
 				if (ctrl_bit.is_fully_const()) {
 					if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit)
@@ -112,8 +112,8 @@ struct FsmOpt
 	{
 		RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"];
 
-		for (int i = 0; i < ctrl_in.__width; i++)
-		for (int j = i+1; j < ctrl_in.__width; j++)
+		for (int i = 0; i < ctrl_in.size(); i++)
+		for (int j = i+1; j < ctrl_in.size(); j++)
 			if (ctrl_in.extract(i, 1) == ctrl_in.extract(j, 1))
 			{
 				log("  Optimize handling of signal %s that is connected to inputs %d and %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j);
@@ -150,8 +150,8 @@ struct FsmOpt
 		RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"];
 		RTLIL::SigSpec &ctrl_out = cell->connections["\\CTRL_OUT"];
 
-		for (int j = 0; j < ctrl_out.__width; j++)
-		for (int i = 0; i < ctrl_in.__width; i++)
+		for (int j = 0; j < ctrl_out.size(); j++)
+		for (int i = 0; i < ctrl_in.size(); i++)
 			if (ctrl_in.extract(i, 1) == ctrl_out.extract(j, 1))
 			{
 				log("  Optimize handling of signal %s that is connected to input %d and output %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j);
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index 6b1753060..718b97043 100644
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -143,15 +143,15 @@ struct FsmData
 		log("  Input signals:\n");
 		RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"];
 		sig_in.expand();
-		for (size_t i = 0; i < sig_in.__chunks.size(); i++)
-			log("  %3zd: %s\n", i, log_signal(sig_in.__chunks[i]));
+		for (size_t i = 0; i < sig_in.chunks().size(); i++)
+			log("  %3zd: %s\n", i, log_signal(sig_in.chunks()[i]));
 
 		log("\n");
 		log("  Output signals:\n");
 		RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"];
 		sig_out.expand();
-		for (size_t i = 0; i < sig_out.__chunks.size(); i++)
-			log("  %3zd: %s\n", i, log_signal(sig_out.__chunks[i]));
+		for (size_t i = 0; i < sig_out.chunks().size(); i++)
+			log("  %3zd: %s\n", i, log_signal(sig_out.chunks()[i]));
 
 		log("\n");
 		log("  State encoding:\n");