iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	195	-729/+729
*	Added opt_const -clkinv	Clifford Wolf	2015-07-01	2	-6/+95
*	Added logic-loop error handling to freduce	Clifford Wolf	2015-06-30	1	-0/+11
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2015-06-30	3	-33/+145
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\| *	Added YosysJS.create_worker()	Clifford Wolf	2015-06-28	3	-33/+145
* \|	Bugfix in chparam	Clifford Wolf	2015-06-30	1	-6/+5
* \|	Added design->rename(module, new_name)	Clifford Wolf	2015-06-30	3	-3/+9
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*	iCE40: set min bram efficiency to 2%	Clifford Wolf	2015-06-20	1	-2/+2
*	Using static mem size of 128 MB in emcc build	Clifford Wolf	2015-06-20	1	-1/+1
*	Added init support to SMV back-end	Clifford Wolf	2015-06-19	1	-1/+3
*	Progress in SMV back-end	Clifford Wolf	2015-06-19	1	-64/+115
*	Progress in SMV back-end	Clifford Wolf	2015-06-19	2	-14/+60
*	Progress in SMV back-end	Clifford Wolf	2015-06-18	4	-24/+147
*	Progress in SMV back-end	Clifford Wolf	2015-06-17	1	-11/+72
*	Added "rename -top new_name"	Clifford Wolf	2015-06-17	3	-0/+43
*	Progress in SMV back-end	Clifford Wolf	2015-06-17	1	-11/+64
*	Progress in SMV back-end	Clifford Wolf	2015-06-16	1	-3/+46
*	Added "synth -nordff -noalumacc"	Clifford Wolf	2015-06-15	1	-3/+20
*	Progress in SMV back-end	Clifford Wolf	2015-06-15	1	-2/+95
*	Progress in SMV back-end	Clifford Wolf	2015-06-15	1	-7/+85
*	Added "write_smv" skeleton	Clifford Wolf	2015-06-15	3	-2/+265
*	Removed debug code from write_smt2	Clifford Wolf	2015-06-14	1	-2/+0
*	Modernized memory_dff (and fixed a bug)	Clifford Wolf	2015-06-14	2	-151/+166
*	Added "memory -nordff"	Clifford Wolf	2015-06-14	1	-2/+9
*	Added write_smt2 -mem	Clifford Wolf	2015-06-14	1	-80/+157
*	Makefile fix for YosysJS build	Clifford Wolf	2015-06-11	1	-0/+4
*	Fixed cstr_buf for std::string with small string optimization	Clifford Wolf	2015-06-11	6	-5/+16
*	Improvements in cellaigs.cc and "json -aig"	Clifford Wolf	2015-06-11	2	-10/+215
*	AigMaker refactoring	Clifford Wolf	2015-06-10	4	-78/+153
*	Added "json -aig"	Clifford Wolf	2015-06-10	3	-9/+76
*	Renamed "aig" to "aigmap"	Clifford Wolf	2015-06-10	3	-10/+10
*	Fixed cellaigs port extending	Clifford Wolf	2015-06-10	3	-3/+11
*	Added "aig" pass	Clifford Wolf	2015-06-09	3	-16/+291
*	synth_ice40 now flattens by default	Clifford Wolf	2015-06-09	1	-4/+8
*	Added cellaigs API	Clifford Wolf	2015-06-09	4	-2/+173
*	Merge clock inverters in memory_dff	Clifford Wolf	2015-06-09	1	-16/+37
*	Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys	Clifford Wolf	2015-06-09	1	-54/+110
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\| *	$mem cell in verilog backend : grouped writes by clock	luke whittlesey	2015-06-08	2	-58/+110
\| *	Bug fix in $mem verilog backend + changed tests/bram flow of make test.	luke whittlesey	2015-06-04	2	-16/+20
* \|	Fixed "avail_parameters" handling in module clone/copy	Clifford Wolf	2015-06-08	1	-0/+2
* \|	Added log_dump() support for IdStrings	Clifford Wolf	2015-06-08	2	-0/+5
* \|	Fixed handling of parameters with reversed range	Clifford Wolf	2015-06-08	1	-1/+1
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*	Added opt_share -share_all	Clifford Wolf	2015-05-31	2	-16/+32
*	Added iCE40 PLL cells	Clifford Wolf	2015-05-31	1	-0/+168
*	Added liberty dont_use support to dfflibmap	Clifford Wolf	2015-05-31	1	-0/+4
*	Fixed signedness of genvar expressions	Clifford Wolf	2015-05-29	1	-2/+2
*	Added output args to synth_ice40	Clifford Wolf	2015-05-26	2	-2/+37
*	Improvements in BLIF front-end	Clifford Wolf	2015-05-24	2	-4/+51
*	improved ice40 SB_IO sim model	Clifford Wolf	2015-05-23	1	-16/+9
*	Improved "flatten" handlings of inout ports	Clifford Wolf	2015-05-23	1	-2/+26