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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-02 13:11:01 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-02 13:19:57 +0200 |
| commit | b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 (patch) | |
| tree | fa56668843c23b8d03a0652be802410f888c6384 /passes/fsm | |
| parent | 14412e6c957a34381c33740426b35f7b90a446be (diff) | |
| download | yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.tar.gz yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.tar.bz2 yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.zip | |
More cleanups related to RTLIL::IdString usage
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_export.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 6025de15b..5675dff50 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -26,7 +26,7 @@ static RTLIL::Module *module; static SigMap assign_map; -typedef std::pair<RTLIL::Cell*,std::string> sig2driver_entry_t; +typedef std::pair<RTLIL::Cell*, RTLIL::IdString> sig2driver_entry_t; static SigSet<sig2driver_entry_t> sig2driver, sig2user; static std::set<RTLIL::Cell*> muxtree_cells; static SigPool sig_at_port; diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index f6f9faa9b..97ccf91ea 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -62,7 +62,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st } else { kiss_name.assign(module->name); - kiss_name.append('-' + cell->name + ".kiss2"); + kiss_name.append('-' + cell->name.str() + ".kiss2"); } log("\n"); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index cf2075fba..5e71c1f0c 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -31,7 +31,7 @@ static RTLIL::Module *module; static SigMap assign_map; -typedef std::pair<std::string, std::string> sig2driver_entry_t; +typedef std::pair<RTLIL::IdString, RTLIL::IdString> sig2driver_entry_t; static SigSet<sig2driver_entry_t> sig2driver, sig2trigger; static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL) @@ -277,7 +277,7 @@ static void extract_fsm(RTLIL::Wire *wire) fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1); fsm_cell->setPort("\\CTRL_IN", ctrl_in); fsm_cell->setPort("\\CTRL_OUT", ctrl_out); - fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); + fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str()); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); |