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author | Clifford Wolf <clifford@clifford.at> | 2014-12-26 10:53:21 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-12-26 10:53:21 +0100 |
commit | a6c96b986be313368b4fa03eba5cf6987448100c (patch) | |
tree | edb56a97a9c64376e1ee920133c46aeefe539ef1 /passes/fsm | |
parent | e8c12e5f0c49cca4dd54da12003bd010a488aee3 (diff) | |
download | yosys-a6c96b986be313368b4fa03eba5cf6987448100c.tar.gz yosys-a6c96b986be313368b4fa03eba5cf6987448100c.tar.bz2 yosys-a6c96b986be313368b4fa03eba5cf6987448100c.zip |
Added Yosys::{dict,nodict,vector} container types
Diffstat (limited to 'passes/fsm')
-rw-r--r-- | passes/fsm/fsm_export.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 668fe8d1d..ad9270334 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -50,7 +50,7 @@ std::string kiss_convert_signal(const RTLIL::SigSpec &sig) { * @param cell pointer to the FSM cell which should be exported. */ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::string filename, bool origenc) { - std::map<RTLIL::IdString, RTLIL::Const>::iterator attr_it; + dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it; FsmData fsm_data; FsmData::transition_t tr; std::ofstream kiss_file; @@ -145,7 +145,7 @@ struct FsmExportPass : public Pass { } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - std::map<RTLIL::IdString, RTLIL::Const>::iterator attr_it; + dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it; std::string arg; bool flag_noauto = false; std::string filename; |