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| author | Clifford Wolf <clifford@clifford.at> | 2014-11-09 10:44:23 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-11-09 10:44:23 +0100 |
| commit | fe829bdbdc436f425e082ab1cc8c3d276f168945 (patch) | |
| tree | 5d73123ffc07ec247e095c76f65bd4800f567d1b /passes/fsm | |
| parent | cb9e10b4624e6ba6fff215766790e3ff3b82e9a8 (diff) | |
| download | yosys-fe829bdbdc436f425e082ab1cc8c3d276f168945.tar.gz yosys-fe829bdbdc436f425e082ab1cc8c3d276f168945.tar.bz2 yosys-fe829bdbdc436f425e082ab1cc8c3d276f168945.zip | |
Added log_warning() API
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 84932e963..c89553c6b 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -43,7 +43,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig return true; if (recursion_monitor.check_any(sig)) { - log("Warning: logic loop in mux tree at signal %s in module %s.\n", + log_warning("logic loop in mux tree at signal %s in module %s.\n", log_signal(sig), RTLIL::id2cstr(module->name)); return false; } |