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* Added liberty parser support for types within cell declsClifford Wolf2016-09-231-39/+46
* Added $past, $stable, $rose, $fell SVA functionsClifford Wolf2016-09-192-2/+141
* Added support for bus interfaces to "read_liberty -lib"Clifford Wolf2016-09-181-1/+77
* Added assertpmuxClifford Wolf2016-09-071-0/+1
* Bugfix in parsing of BLIF latch init valuesClifford Wolf2016-09-061-1/+1
* Avoid creation of bogus initial blocks for assert/assume in always @*Clifford Wolf2016-09-063-1/+13
* Added $anyconst support to yosys-smtbmcClifford Wolf2016-08-301-0/+2
* Removed $aconst cell typeClifford Wolf2016-08-303-6/+6
* Removed $predict againClifford Wolf2016-08-286-14/+3
* Added read_verilog -norestrict -assume-assertsClifford Wolf2016-08-264-5/+40
* Improved verilog parser errorsClifford Wolf2016-08-251-0/+3
* Added SV "restrict" keywordClifford Wolf2016-08-241-1/+2
* Fixed bug with memories that do not have a down-to-zero data widthClifford Wolf2016-08-221-2/+13
* Another bugfix in mem2reg codeClifford Wolf2016-08-213-7/+31
* Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()Clifford Wolf2016-08-211-4/+15
* Fixed finish_addr handling in $readmemh/$readmembClifford Wolf2016-08-201-3/+3
* Optimize memory address port width in wreduce and memory_collect, not verilog...Clifford Wolf2016-08-192-4/+13
* Only allow posedge/negedge with 1 bit wide signalsClifford Wolf2016-08-101-0/+2
* Fixed bug in parsing real constantsClifford Wolf2016-08-061-4/+4
* Added $anyconst and $aconstClifford Wolf2016-07-273-1/+50
* Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-273-9/+30
* Fixed a verilog parser memory leakClifford Wolf2016-07-251-0/+1
* Fixed parsing of empty positional cell portsClifford Wolf2016-07-251-2/+31
* No tristate warning message for "read_verilog -lib"Clifford Wolf2016-07-233-8/+11
* Using $initstate in "initial assume" and "initial assert"Clifford Wolf2016-07-211-1/+6
* Added $initstate cell type and vlog functionClifford Wolf2016-07-212-0/+26
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-216-12/+16
* Added basic support for $expect cellsClifford Wolf2016-07-136-8/+25
* Fixed mem assignment in left-hand-side concatenationClifford Wolf2016-07-081-0/+44
* Allow defining input ports as "input logic" in SystemVerilogRuben Undheim2016-06-201-2/+2
* Merge branch 'sv_packages' of https://github.com/rubund/yosysClifford Wolf2016-06-195-1/+49
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| * A few modifications after pull request commentsRuben Undheim2016-06-181-2/+2
| * Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-185-1/+49
* | Added "read_blif -sop"Clifford Wolf2016-06-181-5/+10
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* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-172-24/+80
* Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}Clifford Wolf2016-05-271-0/+11
* Fixed access-after-delete bug in mem2reg codeClifford Wolf2016-05-272-6/+23
* fixed typos in error messagesClifford Wolf2016-05-271-3/+3
* Small improvements in Verilog front-end docsClifford Wolf2016-05-201-0/+3
* Include <cmath> in yosys.hClifford Wolf2016-05-081-9/+0
* Added support for "active high" and "active low" latches in BLIF front-endClifford Wolf2016-04-221-0/+4
* Added "yosys -D" featureClifford Wolf2016-04-217-8/+8
* Fixed handling of parameters and const functions in casex/casez patternClifford Wolf2016-04-215-8/+37
* Do not set "nosync" on task outputs, fixes #134Clifford Wolf2016-03-241-1/+2
* Added support for $stop system taskClifford Wolf2016-03-211-5/+5
* Added $display %m support, fixed mem leak in $display, fixes #128Clifford Wolf2016-03-191-20/+44
* Fixed localparam signdness, fixes #127Clifford Wolf2016-03-181-1/+1
* Set "nosync" attribute on internal task/function wiresClifford Wolf2016-03-181-0/+1
* Fixed Verilog parser fix and more similar improvementsClifford Wolf2016-03-151-18/+9
* Use left-recursive rule for cell_port_list in Verilog parser.Andrew Becker2016-03-151-6/+10