aboutsummaryrefslogtreecommitdiffstats
path: root/CHANGELOG
Commit message (Collapse)AuthorAgeFilesLines
* Next dev cycleMiodrag Milanovic2022-08-031-0/+3
|
* Release version 0.20Miodrag Milanovic2022-08-031-1/+1
|
* Update ChangelogMiodrag Milanovic2022-08-031-0/+7
|
* Update manual and changelogMiodrag Milanovic2022-08-031-0/+6
|
* Next dev cycleMiodrag Milanovic2022-07-041-0/+3
|
* Release version 0.19Miodrag Milanovic2022-07-041-1/+1
|
* Mention smtlib2_module in README.md and CHANGELOGJannis Harder2022-07-041-3/+4
|
* Upadte documentation and changelogMiodrag Milanovic2022-07-041-0/+15
|
* Next dev cycleMiodrag Milanovic2022-06-101-0/+3
|
* Release version 0.18Miodrag Milanovic2022-06-101-1/+1
|
* Updated CHANGELOGMiodrag Milanovic2022-06-101-0/+3
|
* verific: Added "-vlog-libext" option to specify search extension for librariesMiodrag Milanovic2022-06-091-0/+1
|
* More updates on CHANGELOGMiodrag Milanovic2022-06-081-5/+9
|
* Update changelog and manualMiodrag Milanovic2022-06-081-0/+10
|
* verilog: fix width/sign detection for functionsZachary Snow2022-05-301-0/+2
|
* verilog: fix size and signedness of array querying functionsJannis Harder2022-05-301-0/+2
| | | | | | | | | | genrtlil.cc and simplify.cc had inconsistent and slightly broken handling of signedness for array querying functions. These functions are defined to return a signed result. Simplify always produced an unsigned and genrtlil always a signed 32-bit result ignoring the context. Includes tests for the the relvant edge cases for context dependent conversions.
* verilog: fix $past's signednessJannis Harder2022-05-251-0/+3
|
* verilog: fix signedness when removing unreachable casesJannis Harder2022-05-241-0/+5
|
* Next dev cycleMiodrag Milanovic2022-05-091-0/+3
|
* Release version 0.17Miodrag Milanovic2022-05-091-1/+1
|
* Update CHANGELOGMiodrag Milanovic2022-05-091-0/+3
|
* sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-051-0/+4
|
* Next dev cycleMiodrag Milanovic2022-04-051-0/+3
|
* Release version 0.16Miodrag Milanovic2022-04-051-1/+1
|
* Update CHANGELOG and manualMiodrag Milanovic2022-04-041-0/+9
|
* Next dev cycleMiodrag Milanovic2022-03-041-0/+3
|
* Release version 0.15Miodrag Milanovic2022-03-041-1/+1
|
* Update CHANGELOGMiodrag Milanovic2022-03-021-0/+12
|
* verilog: support for time scale delay valuesZachary Snow2022-02-141-0/+1
|
* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-141-0/+3
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-111-0/+2
|
* verilog: fix const func eval with upto variablesZachary Snow2022-02-111-0/+4
|
* Next dev cycleMiodrag Milanovic2022-02-071-0/+3
|
* Release version 0.14Miodrag Milanovic2022-02-071-1/+1
|
* Update CHANGELOG and manualMiodrag Milanovic2022-02-071-0/+12
|
* Next dev cycleMiodrag Milanovic2022-01-111-0/+3
|
* Release version 0.13Miodrag Milanovic2022-01-111-1/+1
|
* Update CHANGELOGMiodrag Milanovic2022-01-111-6/+19
|
* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-071-0/+3
| | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* sv: fix size cast internal expression extensionZachary Snow2022-01-071-0/+2
|
* sv: fix size cast clipping expression widthZachary Snow2022-01-031-0/+2
|
* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-171-0/+2
| | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* Next dev cycleMiodrag Milanovic2021-12-031-0/+3
|
* Release version 0.12Miodrag Milanovic2021-12-031-1/+1
|
* Update CHANGELOG and CODEOWNERSMiodrag Milanovic2021-12-011-0/+21
|
* Next dev cycleMiodrag Milanovic2021-11-051-0/+3
|
* Release version 0.11Miodrag Milanovic2021-11-051-1/+1
|
* Add missing changelog itemMiodrag Milanovic2021-11-051-0/+1
|
* Add missing items in CHANGELOGMiodrag Milanovic2021-10-291-0/+6
|
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-0/+8
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-22 12:06:49 +0000