Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Next dev cycle | Miodrag Milanovic | 2022-08-03 | 1 | -0/+3 |
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* | Release version 0.20 | Miodrag Milanovic | 2022-08-03 | 1 | -1/+1 |
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* | Update Changelog | Miodrag Milanovic | 2022-08-03 | 1 | -0/+7 |
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* | Update manual and changelog | Miodrag Milanovic | 2022-08-03 | 1 | -0/+6 |
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* | Next dev cycle | Miodrag Milanovic | 2022-07-04 | 1 | -0/+3 |
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* | Release version 0.19 | Miodrag Milanovic | 2022-07-04 | 1 | -1/+1 |
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* | Mention smtlib2_module in README.md and CHANGELOG | Jannis Harder | 2022-07-04 | 1 | -3/+4 |
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* | Upadte documentation and changelog | Miodrag Milanovic | 2022-07-04 | 1 | -0/+15 |
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* | Next dev cycle | Miodrag Milanovic | 2022-06-10 | 1 | -0/+3 |
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* | Release version 0.18 | Miodrag Milanovic | 2022-06-10 | 1 | -1/+1 |
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* | Updated CHANGELOG | Miodrag Milanovic | 2022-06-10 | 1 | -0/+3 |
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* | verific: Added "-vlog-libext" option to specify search extension for libraries | Miodrag Milanovic | 2022-06-09 | 1 | -0/+1 |
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* | More updates on CHANGELOG | Miodrag Milanovic | 2022-06-08 | 1 | -5/+9 |
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* | Update changelog and manual | Miodrag Milanovic | 2022-06-08 | 1 | -0/+10 |
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* | verilog: fix width/sign detection for functions | Zachary Snow | 2022-05-30 | 1 | -0/+2 |
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* | verilog: fix size and signedness of array querying functions | Jannis Harder | 2022-05-30 | 1 | -0/+2 |
| | | | | | | | | | | genrtlil.cc and simplify.cc had inconsistent and slightly broken handling of signedness for array querying functions. These functions are defined to return a signed result. Simplify always produced an unsigned and genrtlil always a signed 32-bit result ignoring the context. Includes tests for the the relvant edge cases for context dependent conversions. | ||||
* | verilog: fix $past's signedness | Jannis Harder | 2022-05-25 | 1 | -0/+3 |
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* | verilog: fix signedness when removing unreachable cases | Jannis Harder | 2022-05-24 | 1 | -0/+5 |
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* | Next dev cycle | Miodrag Milanovic | 2022-05-09 | 1 | -0/+3 |
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* | Release version 0.17 | Miodrag Milanovic | 2022-05-09 | 1 | -1/+1 |
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* | Update CHANGELOG | Miodrag Milanovic | 2022-05-09 | 1 | -0/+3 |
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* | sv: fix always_comb auto nosync for nested and function blocks | Zachary Snow | 2022-04-05 | 1 | -0/+4 |
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* | Next dev cycle | Miodrag Milanovic | 2022-04-05 | 1 | -0/+3 |
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* | Release version 0.16 | Miodrag Milanovic | 2022-04-05 | 1 | -1/+1 |
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* | Update CHANGELOG and manual | Miodrag Milanovic | 2022-04-04 | 1 | -0/+9 |
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* | Next dev cycle | Miodrag Milanovic | 2022-03-04 | 1 | -0/+3 |
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* | Release version 0.15 | Miodrag Milanovic | 2022-03-04 | 1 | -1/+1 |
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* | Update CHANGELOG | Miodrag Milanovic | 2022-03-02 | 1 | -0/+12 |
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* | verilog: support for time scale delay values | Zachary Snow | 2022-02-14 | 1 | -0/+1 |
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* | Fix access to whole sub-structs (#3086) | Kamil Rakoczy | 2022-02-14 | 1 | -0/+3 |
| | | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||||
* | verilog: fix dynamic dynamic range asgn elab | Zachary Snow | 2022-02-11 | 1 | -0/+2 |
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* | verilog: fix const func eval with upto variables | Zachary Snow | 2022-02-11 | 1 | -0/+4 |
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* | Next dev cycle | Miodrag Milanovic | 2022-02-07 | 1 | -0/+3 |
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* | Release version 0.14 | Miodrag Milanovic | 2022-02-07 | 1 | -1/+1 |
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* | Update CHANGELOG and manual | Miodrag Milanovic | 2022-02-07 | 1 | -0/+12 |
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* | Next dev cycle | Miodrag Milanovic | 2022-01-11 | 1 | -0/+3 |
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* | Release version 0.13 | Miodrag Milanovic | 2022-01-11 | 1 | -1/+1 |
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* | Update CHANGELOG | Miodrag Milanovic | 2022-01-11 | 1 | -6/+19 |
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* | sv: auto add nosync to certain always_comb local vars | Zachary Snow | 2022-01-07 | 1 | -0/+3 |
| | | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated. | ||||
* | sv: fix size cast internal expression extension | Zachary Snow | 2022-01-07 | 1 | -0/+2 |
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* | sv: fix size cast clipping expression width | Zachary Snow | 2022-01-03 | 1 | -0/+2 |
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* | fix width detection of array querying function in case and case item expressions | Zachary Snow | 2021-12-17 | 1 | -0/+2 |
| | | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`. | ||||
* | Next dev cycle | Miodrag Milanovic | 2021-12-03 | 1 | -0/+3 |
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* | Release version 0.12 | Miodrag Milanovic | 2021-12-03 | 1 | -1/+1 |
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* | Update CHANGELOG and CODEOWNERS | Miodrag Milanovic | 2021-12-01 | 1 | -0/+21 |
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* | Next dev cycle | Miodrag Milanovic | 2021-11-05 | 1 | -0/+3 |
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* | Release version 0.11 | Miodrag Milanovic | 2021-11-05 | 1 | -1/+1 |
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* | Add missing changelog item | Miodrag Milanovic | 2021-11-05 | 1 | -0/+1 |
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* | Add missing items in CHANGELOG | Miodrag Milanovic | 2021-10-29 | 1 | -0/+6 |
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* | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 1 | -0/+8 |
| | | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change |