index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
Files
Lines
*
Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
Eddie Hung
2019-11-23
3
-11
/
+11
|
\
|
*
Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
Eddie Hung
2019-11-23
5
-13
/
+53
|
|
\
|
|
*
Another sloppy mistake!
Eddie Hung
2019-11-21
1
-1
/
+1
|
|
*
Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
Eddie Hung
2019-11-21
7
-13
/
+22
|
|
|
\
|
|
|
/
|
|
/
|
|
|
*
async2sync -> clk2fflogic
Eddie Hung
2019-11-21
1
-1
/
+1
*
|
|
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
3
-1
/
+1
|
\
\
\
|
*
|
|
Move clkpart into passes/hierarchy
Eddie Hung
2019-11-22
3
-1
/
+1
*
|
|
|
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
2
-51
/
+39
|
\
\
\
\
|
*
|
|
|
Remove redundant flatten
Eddie Hung
2019-11-22
1
-2
/
+0
|
*
|
|
|
submod to bitty rather bussy, for bussy wires used as input and output
Eddie Hung
2019-11-22
1
-48
/
+39
|
*
|
|
|
Stray dump
Eddie Hung
2019-11-22
1
-1
/
+0
*
|
|
|
|
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
2
-2
/
+38
|
\
|
|
|
|
|
*
|
|
|
Constant driven signals are also an input to submodules
Eddie Hung
2019-11-22
1
-2
/
+10
|
*
|
|
|
Add another test with constant driver
Eddie Hung
2019-11-22
1
-0
/
+28
*
|
|
|
|
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
1
-1
/
+0
|
\
|
|
|
|
|
*
|
|
|
Oops
Eddie Hung
2019-11-22
1
-1
/
+0
*
|
|
|
|
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
1
-8
/
+9
|
\
\
\
\
\
|
|
|
/
/
/
|
|
/
|
|
|
|
*
|
|
|
Only action if there is more than one clock domain
Eddie Hung
2019-11-22
1
-7
/
+8
|
*
|
|
|
Replace TODO
Eddie Hung
2019-11-22
1
-1
/
+1
*
|
|
|
|
Add testcase for signal used as part input part output
Eddie Hung
2019-11-22
1
-0
/
+5
*
|
|
|
|
write_xaiger back to working with whole modules only
Eddie Hung
2019-11-22
1
-5
/
+2
*
|
|
|
|
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
2
-1
/
+44
|
\
\
\
\
\
|
|
|
/
/
/
|
|
/
|
|
|
|
*
|
|
|
Cleanup spacing
Eddie Hung
2019-11-22
1
-2
/
+1
|
*
|
|
|
sigmap(wire) should inherit port_output status of POs
Eddie Hung
2019-11-22
1
-1
/
+19
|
*
|
|
|
Add testcase
Eddie Hung
2019-11-22
1
-0
/
+26
*
|
|
|
|
Merge branch 'eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
2
-1
/
+2
|
\
\
\
\
\
|
|
|
/
/
/
|
|
/
|
|
|
|
*
|
|
|
Brackets
Eddie Hung
2019-11-22
1
-1
/
+1
|
*
|
|
|
Entry in Makefile.inc
Eddie Hung
2019-11-22
1
-0
/
+1
*
|
|
|
|
Merge branch 'eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
15
-23
/
+591
|
\
|
|
|
|
|
*
|
|
|
Add to CHANGELOG
Eddie Hung
2019-11-22
1
-0
/
+1
|
*
|
|
|
New 'clkpart' to {,un}partition design according to clock/enable
Eddie Hung
2019-11-22
1
-0
/
+268
|
|
/
/
/
|
*
|
|
Merge pull request #1517 from YosysHQ/clifford/optmem
Clifford Wolf
2019-11-22
3
-0
/
+146
|
|
\
\
\
|
|
*
|
|
Add "opt_mem" pass
Clifford Wolf
2019-11-22
3
-0
/
+146
|
*
|
|
|
Merge pull request #1515 from YosysHQ/clifford/svastuff
Clifford Wolf
2019-11-22
2
-7
/
+39
|
|
\
\
\
\
|
|
|
/
/
/
|
|
/
|
|
|
|
|
*
|
|
Add Verific support for SVA nexttime properties
Clifford Wolf
2019-11-22
1
-0
/
+22
|
|
*
|
|
Improve handling of verific primitives in "verific -import -V" mode
Clifford Wolf
2019-11-22
1
-2
/
+2
|
|
*
|
|
Add Verific SVA support for "always" properties
Clifford Wolf
2019-11-22
1
-5
/
+15
|
|
/
/
/
|
*
|
|
Merge pull request #1511 from YosysHQ/dave/always
Clifford Wolf
2019-11-22
6
-9
/
+126
|
|
\
\
\
|
|
*
|
|
Update CHANGELOG and README
David Shah
2019-11-22
2
-0
/
+7
|
|
*
|
|
sv: Add tests for SV always types
David Shah
2019-11-21
1
-0
/
+63
|
|
*
|
|
proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
David Shah
2019-11-21
1
-4
/
+16
|
|
*
|
|
sv: Correct parsing of always_comb, always_ff and always_latch
David Shah
2019-11-21
2
-5
/
+40
|
*
|
|
|
gowin: Remove show command from tests.
Marcin Kościelnicki
2019-11-22
1
-1
/
+0
|
*
|
|
|
gowin: Add missing .gitignore entries
Marcin Kościelnicki
2019-11-22
1
-0
/
+2
|
|
/
/
/
|
*
|
|
Merge pull request #1507 from YosysHQ/clifford/verificfixes
Clifford Wolf
2019-11-20
2
-6
/
+9
|
|
\
\
\
|
|
*
|
|
Correctly treat empty modules as blackboxes in Verific
Clifford Wolf
2019-11-20
1
-1
/
+1
|
|
*
|
|
Do not rename VHDL entities to "entity(impl)" when they are top modules
Clifford Wolf
2019-11-20
2
-5
/
+8
|
|
/
/
/
*
|
|
|
Revert "write_xaiger to not use module POs but only write outputs if driven"
Eddie Hung
2019-11-22
1
-23
/
+11
*
|
|
|
Missing endmodule
Eddie Hung
2019-11-22
1
-0
/
+1
*
|
|
|
write_xaiger to not use module POs but only write outputs if driven
Eddie Hung
2019-11-21
1
-11
/
+23
[next]
