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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 15:41:34 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 15:41:34 -0800 |
| commit | 84153288bb7d92c31c1d8873b1257a296ca664ad (patch) | |
| tree | addd036c4f81e9a7f5cf27f845f4ec92db43a673 | |
| parent | 3df191cec5d64c743f8fbb0294d9492c5598bc1b (diff) | |
| download | yosys-84153288bb7d92c31c1d8873b1257a296ca664ad.tar.gz yosys-84153288bb7d92c31c1d8873b1257a296ca664ad.tar.bz2 yosys-84153288bb7d92c31c1d8873b1257a296ca664ad.zip | |
Brackets
| -rw-r--r-- | passes/techmap/clkpart.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/clkpart.cc b/passes/techmap/clkpart.cc index 4fa729250..bf3b5bd30 100644 --- a/passes/techmap/clkpart.cc +++ b/passes/techmap/clkpart.cc @@ -144,7 +144,7 @@ struct ClkPartPass : public Pass { { bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_)); bool this_en_pol = !enable_mode || cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)); - key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E)) : RTLIL::SigSpec())); + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec()); } else continue; |