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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 17:24:45 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 17:24:45 -0800 |
| commit | 2c5dfd802d8323709a96993df4e2745c47d2905b (patch) | |
| tree | b54f1114cba6a2a5fefcebab2072d58b63153683 | |
| parent | 89a4a4d90f7d3229f69e80088531bf228dd500c6 (diff) | |
| parent | 8119383f8198d621e88b54fdd615e352ecc576bb (diff) | |
| download | yosys-2c5dfd802d8323709a96993df4e2745c47d2905b.tar.gz yosys-2c5dfd802d8323709a96993df4e2745c47d2905b.tar.bz2 yosys-2c5dfd802d8323709a96993df4e2745c47d2905b.zip | |
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
| -rw-r--r-- | passes/hierarchy/submod.cc | 12 | ||||
| -rw-r--r-- | tests/various/submod.ys | 28 |
2 files changed, 38 insertions, 2 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 707bc26b3..a1fac9b79 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -33,7 +33,7 @@ struct SubmodWorker CellTypes ct; RTLIL::Design *design; RTLIL::Module *module; - pool<Wire*> outputs; + pool<Wire*> constants, outputs; bool copy_mode; std::string opt_name; @@ -125,7 +125,7 @@ struct SubmodWorker RTLIL::Wire *wire = it.first; wire_flags_t &flags = it.second; - if (wire->port_input) + if (wire->port_input || constants.count(wire)) flags.is_ext_driven = true; if (wire->port_output || outputs.count(wire)) flags.is_ext_used = true; @@ -235,6 +235,14 @@ struct SubmodWorker outputs.insert(c.wire); } } + for (auto wire : module->wires()) { + auto sig = sigmap(wire); + for (auto c : sig.chunks()) { + if (c.wire) + continue; + constants.insert(wire); + } + } if (opt_name.empty()) { diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 271a8edef..a9d3fe672 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -23,3 +23,31 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] b); +(* submod="bar" *) sub s1(a, b[1]); +assign b[0] = 1'b0; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +dump +flatten +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter |