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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 17:00:11 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 17:00:11 -0800 |
| commit | 95af8f56e45e23dd29c9a3992f18eee2fa6ceeb1 (patch) | |
| tree | 004727ddd70de7c2d328e6b0b357afbef90ca27a | |
| parent | 00d76f6cc4ccbf15b188570f0bf0dbd143ce3782 (diff) | |
| download | yosys-95af8f56e45e23dd29c9a3992f18eee2fa6ceeb1.tar.gz yosys-95af8f56e45e23dd29c9a3992f18eee2fa6ceeb1.tar.bz2 yosys-95af8f56e45e23dd29c9a3992f18eee2fa6ceeb1.zip | |
Only action if there is more than one clock domain
| -rw-r--r-- | passes/techmap/clkpart.cc | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/passes/techmap/clkpart.cc b/passes/techmap/clkpart.cc index d8d53536d..8f671c175 100644 --- a/passes/techmap/clkpart.cc +++ b/passes/techmap/clkpart.cc @@ -233,15 +233,16 @@ struct ClkPartPass : public Pass { std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)), std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first))); - for (auto &it : assigned_cells) { - RTLIL::Selection sel(false); - sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end()); + if (assigned_cells.size() > 1) + for (auto &it : assigned_cells) { + RTLIL::Selection sel(false); + sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end()); - RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str()); - Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str())); + RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str()); + Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str())); - design->module(submod)->set_bool_attribute(ID(clkpart)); - } + design->module(submod)->set_bool_attribute(ID(clkpart)); + } } } |