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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 16:58:08 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 16:58:08 -0800 |
| commit | 00d76f6cc4ccbf15b188570f0bf0dbd143ce3782 (patch) | |
| tree | c9622f279a0f7564401860b1b7f7e713bba3222b | |
| parent | 84153288bb7d92c31c1d8873b1257a296ca664ad (diff) | |
| download | yosys-00d76f6cc4ccbf15b188570f0bf0dbd143ce3782.tar.gz yosys-00d76f6cc4ccbf15b188570f0bf0dbd143ce3782.tar.bz2 yosys-00d76f6cc4ccbf15b188570f0bf0dbd143ce3782.zip | |
Replace TODO
| -rw-r--r-- | passes/techmap/clkpart.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/clkpart.cc b/passes/techmap/clkpart.cc index bf3b5bd30..d8d53536d 100644 --- a/passes/techmap/clkpart.cc +++ b/passes/techmap/clkpart.cc @@ -58,7 +58,7 @@ struct ClkPartPass : public Pass { } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { - log_header(design, "Executing CLKPART pass (TODO).\n"); + log_header(design, "Executing CLKPART pass (partition design according to clock domain).\n"); log_push(); clear_flags(); |