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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 16:52:17 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 16:52:17 -0800 |
| commit | 81548d1ef988d10007706c36df5885f8557de74a (patch) | |
| tree | a315b518b571b0d2401ded3f578634f604b039db | |
| parent | 0806b8e398bcf2a6aaaf14c389b2d74c50a9ccab (diff) | |
| download | yosys-81548d1ef988d10007706c36df5885f8557de74a.tar.gz yosys-81548d1ef988d10007706c36df5885f8557de74a.tar.bz2 yosys-81548d1ef988d10007706c36df5885f8557de74a.zip | |
write_xaiger back to working with whole modules only
| -rw-r--r-- | backends/aiger/xaiger.cc | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 5d125b653..de2f7dd73 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -545,15 +545,12 @@ struct XAigerWriter undriven_bits.erase(bit); if (!undriven_bits.empty() && !holes_mode) { - bool whole_module = module->design->selected_whole_module(module->name); undriven_bits.sort(); for (auto bit : undriven_bits) { - if (whole_module) - log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit)); + log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit)); input_bits.insert(bit); } - if (whole_module) - log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module)); + log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module)); } if (holes_mode) { |