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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-21 16:33:20 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-21 16:33:20 -0800 |
| commit | 6841e3b1c2b2bc3124810f3a8f96ed00a96e954c (patch) | |
| tree | fb3c0623c1c46fcc4d0c5777472c3fcf9fbdd52e | |
| parent | fe3627523437cfddc069ec9e2c4607a1aaf9ce2e (diff) | |
| download | yosys-6841e3b1c2b2bc3124810f3a8f96ed00a96e954c.tar.gz yosys-6841e3b1c2b2bc3124810f3a8f96ed00a96e954c.tar.bz2 yosys-6841e3b1c2b2bc3124810f3a8f96ed00a96e954c.zip | |
Another sloppy mistake!
| -rw-r--r-- | tests/various/abc9.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/various/abc9.v b/tests/various/abc9.v index 85828bf30..f0b3f6837 100644 --- a/tests/various/abc9.v +++ b/tests/various/abc9.v @@ -13,6 +13,6 @@ endmodule module abc9_test032(input clk, d, r, output reg q); initial q = 1'b0; always @(negedge clk or negedge r) - if (r) q <= 1'b0; + if (!r) q <= 1'b0; else q <= d; endmodule |