diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 17:23:34 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 17:23:34 -0800 |
| commit | 4fdcf8f7d73d0e577815ab50a3e0255f4bfd2154 (patch) | |
| tree | ac8d85b124c89716587a3c9d20640a21625ca2ac | |
| parent | 573396851a03f08f80644924a560369d50659507 (diff) | |
| download | yosys-4fdcf8f7d73d0e577815ab50a3e0255f4bfd2154.tar.gz yosys-4fdcf8f7d73d0e577815ab50a3e0255f4bfd2154.tar.bz2 yosys-4fdcf8f7d73d0e577815ab50a3e0255f4bfd2154.zip | |
Add another test with constant driver
| -rw-r--r-- | tests/various/submod.ys | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 271a8edef..a9d3fe672 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -23,3 +23,31 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] b); +(* submod="bar" *) sub s1(a, b[1]); +assign b[0] = 1'b0; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +dump +flatten +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter |