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authorEddie Hung <eddie@fpgeh.com>2019-11-22 15:41:48 -0800
committerEddie Hung <eddie@fpgeh.com>2019-11-22 15:41:48 -0800
commit698854955cc3ba3fa575f434c29db9e37dcb09b2 (patch)
tree729a0860dc85ed3aba8d05509939029b01af6da9
parentbd56161775f47a474aaf5153d2273b86dad4f6f4 (diff)
parent84153288bb7d92c31c1d8873b1257a296ca664ad (diff)
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Merge branch 'eddie/clkpart' into xaig_dff
-rw-r--r--passes/techmap/Makefile.inc1
-rw-r--r--passes/techmap/clkpart.cc2
2 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index cd357d72a..13992315e 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -41,6 +41,7 @@ OBJS += passes/techmap/zinit.o
OBJS += passes/techmap/dff2dffs.o
OBJS += passes/techmap/flowmap.o
OBJS += passes/techmap/extractinv.o
+OBJS += passes/techmap/clkpart.o
endif
GENFILES += passes/techmap/techmap.inc
diff --git a/passes/techmap/clkpart.cc b/passes/techmap/clkpart.cc
index 4fa729250..bf3b5bd30 100644
--- a/passes/techmap/clkpart.cc
+++ b/passes/techmap/clkpart.cc
@@ -144,7 +144,7 @@ struct ClkPartPass : public Pass {
{
bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
bool this_en_pol = !enable_mode || cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
- key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E)) : RTLIL::SigSpec()));
+ key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec());
}
else
continue;