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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 16:41:05 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 16:48:11 -0800 |
| commit | 2ef2e2c040d9ff299f1bc6daca891a1236ed877e (patch) | |
| tree | bbe8452dc6d747c6138d517e86a37e57de0dc2f5 | |
| parent | c03b6a3e9cab9fc05b2d5b256676f5ddc6c2d763 (diff) | |
| download | yosys-2ef2e2c040d9ff299f1bc6daca891a1236ed877e.tar.gz yosys-2ef2e2c040d9ff299f1bc6daca891a1236ed877e.tar.bz2 yosys-2ef2e2c040d9ff299f1bc6daca891a1236ed877e.zip | |
Add testcase
| -rw-r--r-- | tests/various/submod.ys | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys new file mode 100644 index 000000000..54455b580 --- /dev/null +++ b/tests/various/submod.ys @@ -0,0 +1,26 @@ +read_verilog <<EOT +module top(input a, output [1:0] b); +wire c; +(* submod="bar" *) sub s1(a, c); +assign b[0] = c; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold +submod +flatten + +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + |