| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clkpart to use 'submod -hidden' | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
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| * | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -20/+40 |
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| * | Fold loop | Eddie Hung | 2019-11-25 | 1 | -6/+3 |
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| * | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-25 | 1 | -1/+1 |
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| * | Fix debug | Eddie Hung | 2019-11-25 | 1 | -3/+3 |
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| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 10 | -18/+83 |
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| | * | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 4 | -6/+69 |
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| | * | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 5 | -10/+14 |
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| | * | Merge pull request #1520 from pietrmar/fix-1463 | Eddie Hung | 2019-11-22 | 1 | -2/+0 |
| | |\ | | | | | | | coolrunner2: remove spurious log_pop() call, fixes #1463 | ||||
| | | * | coolrunner2: remove spurious log_pop() call, fixes #1463 | Martin Pietryka | 2019-11-23 | 1 | -2/+0 |
| | |/ | | | | | | | | | | | | | This was causing a segmentation fault because there is no accompanying log_push() call so header_count.size() became -1. Signed-off-by: Martin Pietryka <martin@pietryka.at> | ||||
| * | | Special abc9_clock wire to contain only clock signal | Eddie Hung | 2019-11-25 | 1 | -12/+10 |
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| * | | abc9 to contain time call | Eddie Hung | 2019-11-25 | 1 | -1/+1 |
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| * | | abc9 to no longer to clock partitioning, operate on whole modules only | Eddie Hung | 2019-11-25 | 1 | -139/+32 |
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| * | | clkpart to analyse async flops too | Eddie Hung | 2019-11-25 | 1 | -0/+8 |
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| * | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-23 | 1 | -2/+3 |
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| | * | | More oopsies | Eddie Hung | 2019-11-23 | 1 | -2/+3 |
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| * | | | Conditioning abc9 on POs not accurate due to cells | Eddie Hung | 2019-11-23 | 1 | -15/+6 |
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| * | | | For abc9, run clkpart before ff_map and after abc9 | Eddie Hung | 2019-11-23 | 1 | -0/+2 |
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| * | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-23 | 1 | -13/+27 |
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| | * | | Print ".en=" only if there is an enable signal | Eddie Hung | 2019-11-23 | 1 | -1/+1 |
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| | * | | Escape IdStrings | Eddie Hung | 2019-11-23 | 1 | -3/+2 |
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| | * | | More sane naming of submod | Eddie Hung | 2019-11-23 | 1 | -2/+2 |
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| | * | | Add -set_attr option, -unpart to take attr name | Eddie Hung | 2019-11-23 | 1 | -10/+25 |
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| * | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-23 | 1 | -18/+34 |
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| | * | | Do not use log_signal() for empty SigSpec to prevent "{ }" | Eddie Hung | 2019-11-22 | 1 | -2/+4 |
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| | * | | Call submod once, more meaningful submod names, ignore largest domain | Eddie Hung | 2019-11-22 | 1 | -18/+32 |
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| * | | | Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff | Eddie Hung | 2019-11-23 | 3 | -11/+11 |
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| | * \ \ | Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff | Eddie Hung | 2019-11-23 | 5 | -13/+53 |
| | |\ \ \ | | | | | | | | | | | xaig_dff to support async flops $_DFF_[NP][NP][01]_ | ||||
| | | * | | | Another sloppy mistake! | Eddie Hung | 2019-11-21 | 1 | -1/+1 |
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| | | * | | | Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff | Eddie Hung | 2019-11-21 | 7 | -13/+22 |
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| | | * | | | async2sync -> clk2fflogic | Eddie Hung | 2019-11-21 | 1 | -1/+1 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 3 | -1/+1 |
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| | * | | | | Move clkpart into passes/hierarchy | Eddie Hung | 2019-11-22 | 3 | -1/+1 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -51/+39 |
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| | * | | | | | Remove redundant flatten | Eddie Hung | 2019-11-22 | 1 | -2/+0 |
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| | * | | | | | submod to bitty rather bussy, for bussy wires used as input and output | Eddie Hung | 2019-11-22 | 1 | -48/+39 |
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| | * | | | | | Stray dump | Eddie Hung | 2019-11-22 | 1 | -1/+0 |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -2/+38 |
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| | * | | | | | Constant driven signals are also an input to submodules | Eddie Hung | 2019-11-22 | 1 | -2/+10 |
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| | * | | | | | Add another test with constant driver | Eddie Hung | 2019-11-22 | 1 | -0/+28 |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -1/+0 |
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| | * | | | | | Oops | Eddie Hung | 2019-11-22 | 1 | -1/+0 |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -8/+9 |
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| | * | | | | | Only action if there is more than one clock domain | Eddie Hung | 2019-11-22 | 1 | -7/+8 |
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| | * | | | | | Replace TODO | Eddie Hung | 2019-11-22 | 1 | -1/+1 |
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| * | | | | | | Add testcase for signal used as part input part output | Eddie Hung | 2019-11-22 | 1 | -0/+5 |
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| * | | | | | | write_xaiger back to working with whole modules only | Eddie Hung | 2019-11-22 | 1 | -5/+2 |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -1/+44 |
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| | * | | | | | Cleanup spacing | Eddie Hung | 2019-11-22 | 1 | -2/+1 |
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| | * | | | | | sigmap(wire) should inherit port_output status of POs | Eddie Hung | 2019-11-22 | 1 | -1/+19 |
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index : iCE40/yosys | |
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