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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 12:59:34 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 12:59:34 -0800 |
| commit | 6831510f5b436ddf05b8a1cb30b52be67f865de0 (patch) | |
| tree | 5579a5be247ad62c34091e34f7472214aaed1121 | |
| parent | d087024cafbd4daf4f4c378b02ba15d6d3cf03d4 (diff) | |
| download | yosys-6831510f5b436ddf05b8a1cb30b52be67f865de0.tar.gz yosys-6831510f5b436ddf05b8a1cb30b52be67f865de0.tar.bz2 yosys-6831510f5b436ddf05b8a1cb30b52be67f865de0.zip | |
Fix debug
| -rw-r--r-- | passes/techmap/abc9.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 2409f3d91..193103747 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -347,10 +347,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip log_assert(!design->module(ID($__abc9__))); { AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); - reader.parse_xaiger(); + reader.parse_xaiger(box_lookup); } ifs.close(); - Pass::call(design, stringf("write_verilog -noexpr -norename")); + Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected")); design->remove(design->module(ID($__abc9__))); #endif @@ -421,7 +421,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip ifs.close(); #if 0 - Pass::call(design, stringf("write_verilog -noexpr -norename")); + Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected")); #endif log_header(design, "Re-integrating ABC9 results.\n"); |