diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 15:42:07 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 15:42:07 -0800 |
| commit | 7f0914a40896b566a8b1e139438bd585a9ae2b4b (patch) | |
| tree | 980bc9f6ab8560a7cbe8aeab5c6d8a319fb71a37 | |
| parent | 6831510f5b436ddf05b8a1cb30b52be67f865de0 (diff) | |
| download | yosys-7f0914a40896b566a8b1e139438bd585a9ae2b4b.tar.gz yosys-7f0914a40896b566a8b1e139438bd585a9ae2b4b.tar.bz2 yosys-7f0914a40896b566a8b1e139438bd585a9ae2b4b.zip | |
Do not sigmap keep bits inside write_xaiger
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index de2f7dd73..763a14909 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -183,7 +183,7 @@ struct XAigerWriter } if (keep) - keep_bits.insert(bit); + keep_bits.insert(wirebit); if (wire->port_input || keep) { if (bit != wirebit) |