Special abc9_clock wire to contain only clock signal

1 files changed, 10 insertions, 12 deletions

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 9913b229f..29ddf7133 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -62,10 +62,8 @@
 // The purpose of the following FD* rules are to wrap the flop with:
 // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
 //     the connectivity of its basic D-Q flop
-// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
-//     domain (used when partitioning the module so that `abc9' only
-//     performs sequential synthesis (with reachability analysis) correctly on
-//     one domain at a time)
+// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to indicate its clock
+//     signal, used to extract the delay target
 // (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control 
 //     domain (which, combined with this cell type, encodes to `abc9' which
 //     flops may be merged together)
@@ -88,7 +86,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
@@ -103,7 +101,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
@@ -133,7 +131,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -154,7 +152,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -182,7 +180,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -203,7 +201,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -225,7 +223,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
@@ -240,7 +238,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule