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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-23 10:26:55 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-23 10:26:55 -0800 |
| commit | bf1167bc64eba873ceaf3e4a1988a216fb3909c3 (patch) | |
| tree | 87f8b32173e78237f7bbc33f6a9e93f2442cda86 | |
| parent | eb11c06a69c3b50e39cf363926992b40a9c440c3 (diff) | |
| download | yosys-bf1167bc64eba873ceaf3e4a1988a216fb3909c3.tar.gz yosys-bf1167bc64eba873ceaf3e4a1988a216fb3909c3.tar.bz2 yosys-bf1167bc64eba873ceaf3e4a1988a216fb3909c3.zip | |
Conditioning abc9 on POs not accurate due to cells
| -rw-r--r-- | passes/techmap/abc9.cc | 21 |
1 files changed, 6 insertions, 15 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 4b6ec6e11..c2ac4ef7f 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -322,19 +322,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip fprintf(f, "%s\n", abc9_script.c_str()); fclose(f); - bool count_output = false; - for (auto port_name : module->ports) { - RTLIL::Wire *port_wire = module->wire(port_name); - log_assert(port_wire); - if (port_wire->port_output) { - count_output = true; - break; - } - } - + //bool count_output = false; log_push(); - if (count_output) + //if (count_output) { handle_loops(design, module); @@ -736,10 +727,10 @@ clone_lut: design->remove(mapped_mod); } - else - { - log("Don't call ABC as there is nothing to map.\n"); - } + //else + //{ + // log("Don't call ABC as there is nothing to map.\n"); + //} if (cleanup) { |