| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | vhdl: fix some compiler warnings | Tristan Gingold | 2022-11-08 | 2 | -4/+0 |
| * | simul: fix spurious error about multiple drivers | Tristan Gingold | 2022-10-14 | 1 | -0/+2 |
| * | simul: handle delayed attribute | Tristan Gingold | 2022-10-14 | 2 | -6/+66 |
| * | simul: handle last_event and last_active | Tristan Gingold | 2022-10-13 | 1 | -4/+98 |
| * | simul-vhdl_simul: keep default value of collapsed signals | Tristan Gingold | 2022-10-13 | 1 | -1/+10 |
| * | simul-vhdl_elab: fix crash on association with implicit signals | Tristan Gingold | 2022-10-13 | 1 | -1/+4 |
| * | simul: fix a crash due to missing stride | Tristan Gingold | 2022-10-13 | 1 | -5/+7 |
| * | simul: handle guarded concurrent assignments | Tristan Gingold | 2022-10-10 | 1 | -14/+32 |
| * | simul-vhdl_debug: handle state before elaboration | Tristan Gingold | 2022-10-10 | 1 | -0/+8 |
| * | simul: complete concurrent procedure calls | Tristan Gingold | 2022-10-06 | 1 | -27/+38 |
| * | simul: fix initial value of record signals | Tristan Gingold | 2022-10-06 | 1 | -2/+2 |
| * | simul: recompute object alias offsets | Tristan Gingold | 2022-10-06 | 1 | -1/+14 |
| * | simul: fix signal attribute or guard as actual in connections | Tristan Gingold | 2022-10-06 | 2 | -11/+15 |
| * | simul: improve debugger (display of signals value) | Tristan Gingold | 2022-10-06 | 1 | -27/+26 |
| * | simul: handle suspendable procedure call from sensitized process. | Tristan Gingold | 2022-10-05 | 2 | -3/+11 |
| * | simul: finalize empty procedures | Tristan Gingold | 2022-10-01 | 1 | -9/+11 |
| * | simul: minor rewrite | Tristan Gingold | 2022-10-01 | 1 | -3/+2 |
| * | simul: finalize declarations of procedure calls | Tristan Gingold | 2022-10-01 | 1 | -0/+4 |
| * | simul: handle stable attribute | Tristan Gingold | 2022-09-30 | 2 | -5/+44 |
| * | synth: factorize code | Tristan Gingold | 2022-09-30 | 1 | -0/+8 |
| * | simul: create disconnections | Tristan Gingold | 2022-09-30 | 1 | -1/+42 |
| * | simul: handle quiet attribute | Tristan Gingold | 2022-09-29 | 2 | -7/+72 |
| * | simul: factorize code, add sub_signal_type | Tristan Gingold | 2022-09-29 | 4 | -92/+73 |
| * | simul: support guarded signal assignments (WIP) | Tristan Gingold | 2022-09-29 | 1 | -8/+79 |
| * | synth: handle guard signal in debugger | Tristan Gingold | 2022-09-28 | 1 | -56/+65 |
| * | simul: handle last_value attribute | Tristan Gingold | 2022-09-28 | 1 | -1/+23 |
| * | simul: fix handling of labels in next/exit statements | Tristan Gingold | 2022-09-28 | 1 | -4/+13 |
| * | synth: handle null-range loops | Tristan Gingold | 2022-09-28 | 1 | -4/+3 |
| * | simul: handle null signal assignments | Tristan Gingold | 2022-09-27 | 1 | -12/+36 |
| * | simul-vhdl_elab: avoid a crash for null-range signals | Tristan Gingold | 2022-09-26 | 1 | -10/+14 |
| * | synth: handle attributes in configurations | Tristan Gingold | 2022-09-26 | 2 | -2/+4 |
| * | synth: rework error procedure, always pass the instance | Tristan Gingold | 2022-09-25 | 1 | -1/+1 |
| * | simul: gather disconnection specifications, create guard signal | Tristan Gingold | 2022-09-25 | 3 | -33/+191 |
| * | synth: ignore groups and group templates | Tristan Gingold | 2022-09-25 | 1 | -1/+3 |
| * | simul: handle empty procedures | Tristan Gingold | 2022-09-25 | 1 | -1/+9 |
| * | synth: rework association conversions | Tristan Gingold | 2022-09-25 | 1 | -34/+11 |
| * | simul: reuse drivers extraction from elaboration | Tristan Gingold | 2022-09-25 | 2 | -74/+26 |
| * | synth-vhdl_stmts: minor renaming | Tristan Gingold | 2022-09-18 | 1 | -2/+2 |
| * | simul: handle individual port associations with expressions | Tristan Gingold | 2022-09-18 | 1 | -1/+5 |
| * | simul: handle type conversions in port associations | Tristan Gingold | 2022-09-18 | 1 | -11/+17 |
| * | simul: fix resolved association | Tristan Gingold | 2022-09-17 | 2 | -2/+3 |
| * | simul: use synth_declarations for processes and procedures | Tristan Gingold | 2022-09-17 | 2 | -5/+4 |
| * | synth: factorize code (reuse synth_constant_declaration) | Tristan Gingold | 2022-09-17 | 2 | -2/+2 |
| * | synth: handle protected types in subprograms | Tristan Gingold | 2022-09-17 | 1 | -31/+3 |
| * | synth: preliminary work to factorize code | Tristan Gingold | 2022-09-16 | 1 | -13/+5 |
| * | simul: handle active attribute | Tristan Gingold | 2022-09-16 | 1 | -10/+49 |
| * | simul: improve support of concurrent procedure call | Tristan Gingold | 2022-09-16 | 1 | -1/+20 |
| * | simul: improve error handling during elaboration | Tristan Gingold | 2022-09-16 | 1 | -0/+1 |
| * | simul: handle more signals types | Tristan Gingold | 2022-09-15 | 2 | -23/+128 |
| * | simul: factorize code for conversion functions | Tristan Gingold | 2022-09-12 | 1 | -19/+6 |
