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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-06 20:37:36 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-06 20:37:36 +0200 |
| commit | e985ae703948268ba9ee3127a7d8e5b5c188ce6e (patch) | |
| tree | 0a2390f8866a86c31d37012cfceea0a03d453df2 /src/simul | |
| parent | 4c4467cd5449ff3d9a337850309199bd380ce5e0 (diff) | |
| download | ghdl-e985ae703948268ba9ee3127a7d8e5b5c188ce6e.tar.gz ghdl-e985ae703948268ba9ee3127a7d8e5b5c188ce6e.tar.bz2 ghdl-e985ae703948268ba9ee3127a7d8e5b5c188ce6e.zip | |
simul: fix initial value of record signals
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 26c2179ea..e3b624971 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -262,9 +262,9 @@ package body Simul.Vhdl_Simul is end loop; end; when Type_Record => - for I in Val.Typ.Rec.E'Range loop + for I in Target.Typ.Rec.E'Range loop declare - E : Rec_El_Type renames Val.Typ.Rec.E (I); + E : Rec_El_Type renames Target.Typ.Rec.E (I); Smem : Memory_Ptr; begin if Val.Mem = null then |