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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-10 07:44:25 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-10 07:44:25 +0200 |
| commit | e807a08d64c7dbf18edd4a3a99fd1f7cbd655055 (patch) | |
| tree | fbe7cfdb48e89a6ce18b0fbe363e3e8708aa7530 /src/simul | |
| parent | 9fbdffe8e76a9ff1a71e631914bf75f362b36be7 (diff) | |
| download | ghdl-e807a08d64c7dbf18edd4a3a99fd1f7cbd655055.tar.gz ghdl-e807a08d64c7dbf18edd4a3a99fd1f7cbd655055.tar.bz2 ghdl-e807a08d64c7dbf18edd4a3a99fd1f7cbd655055.zip | |
simul-vhdl_debug: handle state before elaboration
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_debug.adb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb index 8edf963d8..8eb2c1cab 100644 --- a/src/simul/simul-vhdl_debug.adb +++ b/src/simul/simul-vhdl_debug.adb @@ -216,6 +216,10 @@ package body Simul.Vhdl_Debug is Sig : Ghdl_Signal_Ptr; begin Sig := Simul.Vhdl_Simul.Read_Sig (S.Mem); + if Sig = null then + Put_Line ("*not yet elaborated*"); + return; + end if; Put_Addr (Sig.all'Address); Put (' '); Grt.Disp_Signals.Disp_Single_Signal_Attributes (Sig); @@ -333,6 +337,10 @@ package body Simul.Vhdl_Debug is Ctxt : Rti_Context; begin Sig := Simul.Vhdl_Simul.Read_Sig (S.Mem); + if Sig = null then + Put_Line ("*not yet elaborated*"); + return; + end if; Put_Addr (Sig.all'Address); Put (' '); Ev := Sig.Event_List; |