| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | Renaming BRAM memory tests for the sake of uniformity | Diego H | 2019-12-13 | 2 | -6/+6 | |
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| | * | | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. | Diego H | 2019-12-12 | 1 | -2/+2 | |
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| | * | | Adding a note (TODO) in the memory_params.ys check file | Diego H | 2019-12-12 | 1 | -0/+2 | |
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| | * | | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 | Diego H | 2019-12-12 | 2 | -0/+90 | |
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| * | | abc9 needs a clean afterwards | Eddie Hung | 2019-12-16 | 1 | -2/+4 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-12 | 3 | -23/+136 | |
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| | * | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr | Eddie Hung | 2019-12-09 | 3 | -23/+136 | |
| | |\ | | | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER | |||||
| | | * | unmap $__ICE40_CARRY_WRAPPER in test | Eddie Hung | 2019-12-09 | 1 | -1/+21 | |
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| | | * | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 1 | -3/+5 | |
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| | | * | Drop keep=0 attributes on SB_CARRY | Eddie Hung | 2019-12-06 | 1 | -2/+2 | |
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| | | * | Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-12-05 | 1 | -0/+30 | |
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| | | * | Check SB_CARRY name also preserved | Eddie Hung | 2019-12-03 | 1 | -0/+1 | |
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| | | * | Add testcase | Eddie Hung | 2019-12-03 | 1 | -0/+60 | |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 6 | -8/+412 | |
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| | * | | tests: arch: xilinx: Change order of arguments in macc.sh | Jan Kowalewski | 2019-12-06 | 1 | -1/+1 | |
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| | * | | iopadmap: Refactor and fix tristate buffer mapping. (#1527) | Marcin Kościelnicki | 2019-12-04 | 1 | -0/+99 | |
| | |/ | | | | | | | | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not). | |||||
| | * | Merge pull request #1524 from pepijndevos/gowindffinit | Clifford Wolf | 2019-12-03 | 3 | -2/+301 | |
| | |\ | | | | | | | Gowin: add and test DFF init values | |||||
| | | * | update test | Pepijn de Vos | 2019-12-03 | 1 | -2/+3 | |
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| | | * | Use -match-init to not synth contradicting init values | Pepijn de Vos | 2019-12-03 | 1 | -10/+12 | |
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| | | * | attempt to fix formatting | Pepijn de Vos | 2019-11-25 | 1 | -138/+138 | |
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| | | * | gowin: add and test dff init values | Pepijn de Vos | 2019-11-25 | 2 | -0/+296 | |
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| | * | | abc9: Fix breaking of SCCs | David Shah | 2019-12-01 | 1 | -0/+6 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | abc9_map.v to transform INIT=1 to INIT=0 | Eddie Hung | 2019-12-04 | 1 | -0/+91 | |
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| * | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -0/+31 | |
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| | * | | | Add multiple driver testcase | Eddie Hung | 2019-11-27 | 1 | -0/+31 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-27 | 2 | -0/+82 | |
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| | * | | | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd | Eddie Hung | 2019-11-27 | 1 | -0/+69 | |
| | |\ \ \ | | | | | | | | | | | xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder | |||||
| | | * | | | No need for -abc9 | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| | | * | | | Add citation | Eddie Hung | 2019-11-26 | 1 | -0/+1 | |
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| | | * | | | Add testcase derived from fastfir_dynamictaps benchmark | Eddie Hung | 2019-11-26 | 1 | -0/+68 | |
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| | * | | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fix | Clifford Wolf | 2019-11-27 | 1 | -0/+13 | |
| | |\ \ \ \ | | | | | | | | | | | | | opt_share: Fix handling of fine cells. | |||||
| | | * | | | | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+13 | |
| | | |/ / / | | | | | | | | | | | | | | | | Fixes #1525. | |||||
| * | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -9/+0 | |
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| | * | | | | Remove notes | Eddie Hung | 2019-11-26 | 1 | -9/+0 | |
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| * | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -2/+23 | |
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| | * | | | Revert "submod to bitty rather bussy, for bussy wires used as input and output" | Eddie Hung | 2019-11-27 | 1 | -2/+5 | |
| | | | | | | | | | | | | | | | | | This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45. | |||||
| | * | | | Fix wire width | Eddie Hung | 2019-11-26 | 1 | -2/+2 | |
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| | * | | | Add testcase where \init is copied | Eddie Hung | 2019-11-25 | 1 | -0/+18 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 5 | -13/+24 | |
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| | * | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -5/+16 | |
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| | * | | | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 4 | -8/+8 | |
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| * | | | Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff | Eddie Hung | 2019-11-23 | 3 | -11/+11 | |
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| | * | | | Another sloppy mistake! | Eddie Hung | 2019-11-21 | 1 | -1/+1 | |
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| | * | | | Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff | Eddie Hung | 2019-11-21 | 3 | -4/+9 | |
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| | * | | | | async2sync -> clk2fflogic | Eddie Hung | 2019-11-21 | 1 | -1/+1 | |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -3/+0 | |
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| | * | | | | Remove redundant flatten | Eddie Hung | 2019-11-22 | 1 | -2/+0 | |
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| | * | | | | Stray dump | Eddie Hung | 2019-11-22 | 1 | -1/+0 | |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+28 | |
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| | * | | | | Add another test with constant driver | Eddie Hung | 2019-11-22 | 1 | -0/+28 | |
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index : iCE40/yosys | |
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