iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add test	Eddie Hung	2019-06-20	1	-0/+11
*	Add proper test for SV-style arrays	Clifford Wolf	2019-06-20	1	-0/+16
*	Add defvalue test, minor autotest fixes for .sv files	Clifford Wolf	2019-06-19	1	-0/+22
*	Rename implicit_ports.sv test to implicit_ports.v	Clifford Wolf	2019-06-07	1	-0/+0
*	Cleanup tux3-implicit_named_connection	Clifford Wolf	2019-06-07	1	-0/+16
*	Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...	Clifford Wolf	2019-06-07	1	-1/+2
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\| *	SystemVerilog support for implicit named port connections	tux3	2019-06-06	1	-1/+2
* \|	Added tests for attributes	Maciej Kurc	2019-06-03	9	-0/+219
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*	Merge pull request #1049 from YosysHQ/clifford/fix1047	Clifford Wolf	2019-05-28	1	-0/+4
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\| *	Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047	Clifford Wolf	2019-05-28	1	-0/+4
* \|	Add actual wandwor test that is part of "make test"	Clifford Wolf	2019-05-28	1	-0/+36
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*	Added tests for Verilog frontent for attributes on parameters and localparams	Maciej Kurc	2019-05-16	2	-0/+22
*	Add test case from #997	Clifford Wolf	2019-05-07	1	-0/+12
*	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968	Clifford Wolf	2019-05-06	3	-0/+32
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\| *	Merge pull request #969 from YosysHQ/clifford/pmgenstuff	Clifford Wolf	2019-05-03	1	-0/+9
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\| \| *	Add peepopt_muldiv, fixes #930	Clifford Wolf	2019-04-30	1	-0/+9
\| * \|	Merge pull request #976 from YosysHQ/clifford/fix974	Clifford Wolf	2019-05-03	1	-0/+22
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\| \| * \|	Add splitcmplxassign test case and silence splitcmplxassign warning	Clifford Wolf	2019-05-01	1	-0/+22
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\| * /	Fix #938 - Crash occurs in case when use write_firrtl command	Jim Lawson	2019-05-01	1	-0/+1
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* /	Add additional test cases for for-loops	Clifford Wolf	2019-05-01	1	-0/+25
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*	Add retime test	Eddie Hung	2019-04-05	1	-0/+6
*	fix local name resolution in prefix constructs	Zachary Snow	2019-03-18	1	-0/+56
*	Fix handling of task output ports in clocked always blocks, fixes #857	Clifford Wolf	2019-03-07	1	-0/+19
*	Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails	Jim Lawson	2019-03-04	1	-0/+1
*	Fix FIRRTL to Verilog process instance subfield assignment.	Jim Lawson	2019-02-25	1	-1/+0
*	Fix handling of defparam for when default_nettype is none	Clifford Wolf	2019-02-24	1	-0/+2
*	Merge https://github.com/YosysHQ/yosys into dff_init	Eddie Hung	2019-02-17	1	-0/+26
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\| *	Update cells supported for verilog to FIRRTL conversion.	Jim Lawson	2019-02-15	1	-0/+26
* \|	Extend testcase	Eddie Hung	2019-02-06	1	-2/+34
* \|	Add testcase	Eddie Hung	2019-02-06	1	-0/+10
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*	Basic test for checking correct synthesis of SystemVerilog interfaces	Ruben Undheim	2018-10-18	1	-90/+0
*	Support for 'modports' for System Verilog interfaces	Ruben Undheim	2018-10-12	1	-3/+17
*	Synthesis support for SystemVerilog interfaces	Ruben Undheim	2018-10-12	1	-0/+76
*	Fix tests/simple/specify.v	Clifford Wolf	2018-03-27	1	-2/+2
*	First draft of Verilog parser support for specify blocks and parameters.	Udi Finkelstein	2018-03-27	1	-0/+31
*	Allow $size and $bits in verilog mode, actually check test case	Clifford Wolf	2017-09-29	1	-32/+0
*	$size() now works correctly for all cases!	Udi Finkelstein	2017-09-26	1	-5/+11
*	$size() seems to work now with or without the optional parameter.	Udi Finkelstein	2017-09-26	1	-8/+18
*	Added $bits() for memories as well.	Udi Finkelstein	2017-09-26	1	-6/+5
*	$size() now works with memories as well!	Udi Finkelstein	2017-09-26	1	-2/+4
*	Add $size() function. At the moment it works only on expressions, not on memo...	Udi Finkelstein	2017-09-26	1	-0/+15
*	Squelch trailing whitespace	Larry Doolittle	2017-04-12	1	-1/+1
*	Fixed typo in tests/simple/arraycells.v	Clifford Wolf	2017-01-04	1	-1/+1
*	Added support for hierarchical defparams	Clifford Wolf	2016-11-15	1	-0/+23
*	Add optional SEED=n command line option to Makefile, and -S n command line op...	Eric Smith	2016-09-22	1	-1/+12
*	Fixed bug with memories that do not have a down-to-zero data width	Clifford Wolf	2016-08-22	1	-0/+30
*	Added another mem2reg test case	Clifford Wolf	2016-08-21	1	-0/+11
*	Another bugfix in mem2reg code	Clifford Wolf	2016-08-21	1	-0/+22
*	Fixed mem assignment in left-hand-side concatenation	Clifford Wolf	2016-07-08	1	-0/+13
*	Fixed init issue in mem2reg_test2 test case	Clifford Wolf	2016-06-17	1	-2/+6