Support for 'modports' for System Verilog interfaces

1 files changed, 17 insertions, 3 deletions

diff --git a/tests/simple/svinterface1.sv b/tests/simple/svinterface1.sv
index 779d50c14..64383a06c 100644
--- a/tests/simple/svinterface1.sv
+++ b/tests/simple/svinterface1.sv
@@ -19,7 +19,7 @@ module TopModule(
 
 
   assign MyInterfaceInstance.setting = 1;
-  assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
+//  assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
 
 endmodule
 
@@ -32,13 +32,25 @@ interface MyInterface #(
 
   logic [1:0] mysig_out;
 
+    modport submodule1 (
+        input  setting,
+        output other_setting,
+        output mysig_out
+    );
+
+    modport submodule2 (
+        input  setting,
+        output other_setting,
+        input  mysig_out
+    );
+
 endinterface
 
 
 module SubModule1(
     input logic clk,
     input logic rst,
-    MyInterface u_MyInterface,
+    MyInterface.submodule1 u_MyInterface,
     input logic [1:0] sig
 
   );
@@ -68,9 +80,11 @@ module SubModule2(
 
     input logic clk,
     input logic rst,
-    MyInterface u_MyInterfaceInSub2,
+    MyInterface.submodule2 u_MyInterfaceInSub2,
     input logic [1:0] sig
 
   );
 
+   assign u_MyInterfaceInSub2.other_setting[2:0] = 9;
+
 endmodule