diff options
| author | Clifford Wolf <clifford@clifford.at> | 2016-08-21 13:45:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-21 13:45:46 +0200 |
| commit | cdd0b85e47d6c1718ec5c0d2d80c87af3e3bbc83 (patch) | |
| tree | 334a3f956e2a1dc4d4c9fe2560238e2bdc66aac0 /tests/simple | |
| parent | 82a4a0230feedd994546ad57a1f4ae79b8f80136 (diff) | |
| download | yosys-cdd0b85e47d6c1718ec5c0d2d80c87af3e3bbc83.tar.gz yosys-cdd0b85e47d6c1718ec5c0d2d80c87af3e3bbc83.tar.bz2 yosys-cdd0b85e47d6c1718ec5c0d2d80c87af3e3bbc83.zip | |
Added another mem2reg test case
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/mem2reg.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index 23094c10a..9839fd4a8 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -81,3 +81,14 @@ module mem2reg_test4(result1, result2, result3); assign result3 = intermediate[depth2Index(3)]; endmodule +// ------------------------------------------------------ + +module mem2reg_test5(input ctrl, output out); + wire [0:0] foo[0:0]; + wire [0:0] bar[0:1]; + + assign foo[0] = ctrl; + assign bar[0] = 0, bar[1] = 1; + assign out = bar[foo[0]]; +endmodule + |